Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
12-42 Freescale Semiconductor
DDR SDRAM Memory Controller
12.7.7 DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG)
DDR_SDRAM_CFG enables the interface logic and specifies certain operating features such as
self refreshing, error checking and correcting and dynamic power management. The default value
is 0b010, designating DDR1 SDRAM.
WRITE_
DATA_
DELAY
12–10
0 Write Data Delay
Controls the amount of delay applied to the data and data
strobes for writes. These bits allow write data to be sent later
than the nominal time to meet the SDRAM timing requirement
between the registration of a write command and the reception
of a data strobe associated with the write command. The
specification dictates that the data strobe may not be received
earlier than 75 percent of a cycle or later than 125 percent of a
cycle from the registration of a write command. This parameter
is not defined in the SDRAM specification and should be
defined according to the system timing. 000 0 clock delay
001 1/4 clock delay
010 1/2 clock delay
011 3/4 clock delay
100 1 clock delay
101 5/4 clock delay
110 3/2 clock delay
111 Reserved
—
9
0 Reserved. Write to zero for future compatibility.
CKE_PLS
8–6
0 Minimum CKE Pulse Width (t
CKE
)
Can be set to 001 for DDR1.
This field must be programmed for proper operation of the DDR
Controller.
000 Reserved.
001 1 clock cycle.
010 2 clock cycles.
011 3 clock cycles.
100 4 clock cycles.
101–111 Reserved
FOUR_ACT
5–0
0 Window for Four Activates (t
FAW
).
This is applied to DDR2 with eight logical banks only.
Must be set to 0001 for DDR1
000000 Reserved.
000001 1 clock cycle.
000010 2 clock cycles.
000011 3 clock cycles.
000100 4 clock cycles.
...
010011 19 clock cycles.
010100 20 clock cycles.
010101–11111 Reserved.
DDR_SDRAM_CFG DDR SDRAM Control Configuration Register Offset 0x0110
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MEMEN SREN
ECC_
EN
— SDRAM_Type —
DYN_
PWR_
MGMT
— 16BE — NCAP —
Type R/W R R/W R R/W R R/W R R/W R
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2T_EN — HSE — MHALT BI
Type R/W R R/W R R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 12-21. TIMING_CFG_2 Bit Descriptions (Continued)
Bit Reset Description Settings