Freescale Semiconductor MSC8144E, Reference Manual

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Memory Controller Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 12-39
CASLAT
19–16
0
MCAS
Latency from READ Command
Specifies the number of clock cycles between the time the
SDRAM registers a READ command and the availability of the
first output data. CASLAT is used in conjunction with additive
latency to obtain the read latency. If a READ command is
registered at clock edge
n
and the latency is
m
clock cycles.,
data is available nominally coincident with clock edge
n
+
m
.
This value must be programmed at initialization as described in
the discussion of the DDR SDRAM Control Configuration
Register (SCFG) on page 12-46.
This field must be programmed for proper operation of the DDR
Controller.
0000 Reserved.
0001 1 clock cycle.
0010 1.5 clock cycles.
0011 2 clock cycles.
0100 2.5 clock cycles.
0101 3 clock cycles.
0110 3.5 clock cycles.
0111 4 clock cycles.
1000 4.5 clock cycles.
1001 5 clock cycles.
1010 5.5 clock cycles.
1011 6 clock cycles.
1100 6.5 clock cycles.
1101 7 clock cycles.
1110 7.5 clock cycles.
1111 8 clock cycles.
REFREC
15–12
0 Refresh Recovery Time (t
RFC
)
Specifies the minimum number of clock cycles between a
refresh command and an activate command. This value can be
calculated by referring to the AC specification of the SDRAM
device. The AC specification indicates a maximum refresh to
activate interval in nanoseconds. This field is concatenated with
TIMING_CFG_3[REFR] to obtain a 7-bit value for the total
refresh recovery. Note that hardware adds an additional 8 clock
cycles to the final 7-bit value of the refresh recovery.
t
RFC
= {TIMING_CFG_3 || REFREC} + 8
min. value = 8 clocks TIMING_CFG_3 = 0x0, REFREC = 0x0
max. value = 135 clocks TIMING_CFG_3 = 0x7, REFREC = 0xF
= 112+15+8
0000 8 clock cycles.
0001 9 clock cycles.
0010 10 clock cycles.
0011 11 clock cycles.
…
1111 23 clock cycles.
—
11
0 Reserved. Write to zero for future compatibility.
WRREC
10–8
0 Write Recovery (t
WR
)
Specifies the minimum number of clock cycles between the last
data associated with a write command and a precharge
command. This interval, write recovery time, is calculated from
the AC specifications of the SDRAM.
This field must be programmed for proper operation of the DDR
Controller.
000 0 clock cycle.
001 1 clock cycle.
010 2 clock cycles.
011 3 clock cycles.
100 4 clock cycles.
101 5 clock cycles.
110 6 clock cycles.
111 7 clock cycles.
—
7
0 Reserved. Write to zero for future compatibility.
Table 12-20. TIMING_CFG_1 Field Descriptions (Continued)
Bits Reset Description Settings