Freescale Semiconductor MSC8144E, Reference Manual

Page: 348 / 1374

MSC8144E Reference Manual, Rev. 3
9-34 Freescale Semiconductor
Memory Map
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0xFFF20114 DDR SDRAM Control Configuration 2 DDR_SDRAM_CFG_2 page 12-44
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0xFFF20118 DDR SDRAM Mode Configuration DDR_SDRAM_MODE page 12-46
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0xFFF2011C DDR SDRAM Mode Configuration 2 DDR_SDRAM_MODE_2 page 12-47
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0xFFF20120 DDR SDRAM Model Control DDR_SCRAM_MD_CNTL page 12-47
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0xFFF20124 DDR SDRAM Interval Configuration DDR_SDRAM_INTERVAL page 12-49
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0xFFF20128 DDR SDRAM Data Initialization DDR_DATA_INIT page 12-50
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0xFFF2012C–
0xFFF2012F reserved
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0xFFF20130 DDR SDRAM Clock Control DDR_SDRAM_CLK_CNT page 12-50
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0xFFF20134–
0xFFF20147 reserved
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0xFFF20148 DDR Training Initialization Address DDR_INIT_ADDRESS page 12-51
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0xFFF2014C DDR Training Initialization Enable DDR_INIT_EN page 12-52
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0xFFF20150–
0xFFF20BF7 reserved
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0xFFF20BF8 DDR IP Block Revision 1 DDR_IP_REV1 page 12-53
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0xFFF20BFC DDR IP Block Revision 2 DDR_IP_REV2 page 12-53
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0xFFF20C00–
0xFFF20DFF reserved
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0xFFF20E00 Memory Data Path Error Injection Mask High DDR_ERR_INJECT_HI page 12-54
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0xFFF20E04 Memory Data Path Error Injection Mask Low DDR_ERR_INJECT_LO page 12-55
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0xFFF20E08 Memory Data Path Error Injection Mask ECC DDR_ERR_INJECT page 12-55
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0xFFF20E0C–
0xFFF20E1F reserved
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0xFFF20E20 Memory Data Path Read Capture High CAPTURE_DATA_HI page 12-56
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0xFFF20E24 Memory Data Path Read Capture Low CAPTURE-DATA_LO page 12-57
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0xFFF20E28 Memory Data Path Read Capture ECC CAPTURE_ECC page 12-57
−
0xFFF20E2C–
0xFFF20E3F reserved
−
0xFFF20E40 Memory Error Detect ERR_DETECT page 12-58
−
0xFFF20E44 Memory Error Disable ERR_DISABLE page 12-59
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0xFFF20E48 Memory Error Interrupt Enable ERR_INT_EN page 12-60
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0xFFF20E4C Memory Error Attributes Capture CAPTURE_ATTRIBUTES page 12-61
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0xFFF20E50 Memory Error Address Capture CAPTURE_ADDRESS page 12-62
−
0xFFF20E54–
0xFFF20E57 reserved
−
0xFFF20E58 Single-Bit ECC Memory Error Management ERR_SBE page 12-62
−
0xFFF20E5C–
0xFFF20FFF reserved
−
0xFFF21000 DDR SDRAM DDR Status DDR_STOP_STATUS page 12-63
−
0xFFF21004 DDR SDRAM DDR Power Control Register DDR_PWR page 12-64
−
0xFFF21008 DDR SDRAM MDIC Output Enable Control Register MDIC_OE_CONT page 12-65
−
0xFFF2100C DDR SDRAM Termination, OCD, and ODT Control Register TERM_OCD_ODT_CONT page 12-66
−
0xFFF21010 DDR SDRAM Clock Ratio Control Register CLK_RATIO_CONT page 12-67
Table 9-9. Consolidated Memory Map (Continued)
Address Name/Status Acronym Reference