RapidIO Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
16-195
16.6.83
Inbound Doorbell Queue Dequeue Pointer Address Register
(IDQDPAR)
IDQDPAR contains the double-word address for the first doorbell in memory to be processed.
Software must initialize this register to the first doorbell entry location in memory. After a
doorbell is processed, the processor sets IDMR[DI]. Then the doorbell queue dequeue pointer
address register is incremented by hardware to point to the next doorbell entry in memory and
IDMR[DI] is cleared.
When processing multiple doorbells, the processor can write this register directly instead of
setting IDMR[DI] for each doorbell. If the enqueue pointer and the dequeue pointer are not equal
(indicating that the queue is not empty), the processor can read the next doorbell from memory
for processing. If the enqueue and dequeue pointers are equal after the processor increments the
IDQDPAR, the queue is empty, and all outstanding doorbells have been processed.
QE
1
1
Queue Empty
If the queue is empty, then this bit is set. This bit will also be set if the doorbell controller is
disabled. Read only.
DIQI
0
0
Doorbell-In-Queue Interrupt
If DIQ is set and IDMR[DIQIE} is set, the controller sets this bit and generates an interrupt. This bit
is cleared by writing a 1 to it.
IDQDPAR
Inbound Doorbell Queue Dequeue Pointer Address Registers Offset 0x1346C
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DQDPA
TYPE
R/W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DQDPA
—
TYPE
R
R
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 16-126. IDQDPAR Field Descriptions
Bits
Reset Description
DQDPA
31–3
0
Doorbell Dequeue Pointer Address
Contains the double-word address of the first doorbell in memory to process.
—
2–0
0
Reserved. Write to zero for future compatibility.
Table 16-125. IDSR Field Descriptions (Continued)
Bits
Reset Description
Summary of Contents for MSC8144E
Page 1: ...MSC8144E Reference Manual Quad Core Media Signal Processor MSC8144ERM Rev 3 July 2009 ...
Page 48: ...MSC8144E Reference Manual Rev 3 xlviii Freescale Semiconductor ...
Page 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Page 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Page 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Page 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Page 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Page 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Page 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Page 1070: ...MSC8144E Reference Manual Rev 3 21 28 Freescale Semiconductor Timers ...
