Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
10-8 Freescale Semiconductor
MSC8144E SC3400 DSP Subsystem
10.7 Dual Timer
Each DSP core subsystem includes two 32-bit general-purpose counters with pre-loading
capability. It counts clocks at the core frequency. The timers are intended mainly for operating
system use.
Note: See Chapter 21, Timers for details about the timers.
10.8 Interfaces
The DSP core subsystem supports separate buses for data and instructions and uses two bridges
(IQ2M and DQ2M) to connect between the core instruction QBus (P lines) and the data QBus
(Xa and Xb lines) used by the SC3400 core and the MBus that connects to the other blocks in the
MSC8144 device. The bridges are placed between two clock domains: internal and external. The
two clock domains are asynchronous. The internal clock domain runs at the core frequency and
the external clock is slower to comply with the other block requirements.
The interfaces include the following:
„
Bus widths
— 128-bit data buses (read/write) for both buses
— 32-bit address bus for both buses
— 8-bit line byte count
„
Frequency reduction from the QBus frequency and the system frequency
„
Bus error interrupt generation
„
Idle indications that allow the extend core to enter STOP mode
„
Burst transactions up to 128 bytes
„
Burst wraparounds on both sides of the bridges (for bursts of two or more beats)
10.9 DSP Core Subsystem Operating States
This section describes the DSP core subsystem processing states. These states are related to the
SC3400 processing states, but include additional platform-specific attributes. The processing
states include:
„
Reset
„
Execution
„
Debug
„
WAIT
„
STOP