Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
12-22 Freescale Semiconductor
DDR SDRAM Memory Controller
Note: For MSC8144E the DDR controller will not perform wrapped accesses. Accesses that
their start address is not aligned to 16 or 8 byte (according to the actual mode) and
crosses the alignment boundary will be split into two accesses toward the memory. For
example a 16 byte access to word offset 1 will result in two bursts one for words 1,2,3
and the second to word 0 of the next group - In any case the memory interface will be
occupied for 8 data beats.
Note: Similar behavior will occur for 16bit memory interface - every “word” mentioned
above should be read a “half word - two bytes”.
12.3.6 Page Mode and Logical Bank Retention
The DDR memory controller supports an open/closed page mode that allows an open page for
each logical bank of DRAM. In closed page mode for DDR SDRAMs, the DDR memory
controller uses the auto-precharge feature, which allows the controller to indicate the DDR
SDRAM that it must automatically close the page after the read or write access. This is
performed by using
MA10
of the address during the
COMMAND
phase of the access to enable
auto-precharge. Auto-precharge is non-persistent in that it is either enabled or disabled for each
individual
READ
or
WRITE
command. However, it can be separately enabled or disabled for each
chip select. In open page mode, the DDR memory controller retains the currently active SDRAM
page by not issuing a precharge command. The page remains opens until one of the following
conditions occurs:
„
Refresh interval is met.
„
The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded.
„
There is a logical bank row collision with another transaction that must be issued.
Page mode can dramatically reduce access latencies for page hits. Depending on the memory
system design and timing parameters, using page mode can save two to three clock cycles for
subsequent burst accesses that hit in an active page. Also, better performance can be obtained by
using more banks, especially in systems which use many different channels. Page mode is
disabled by clearing DDR_SDRAM_INTERVAL[BSTOPRE] or setting
CSx_CONFIG[AP_x_EN].
12.4 Error Checking and Correction
The DDR memory controller supports error checking and correcting (ECC) for the data path
between the core initiator and system memory. The DDR memory controller detects all
double-bit errors in a word, detects all multi-bit errors within a nibble, and it corrects all
single-bit errors in a word. Other errors may be detected, but are not guaranteed to be corrected or
detected. Multiple-bit errors are always reported when error reporting is enabled. When a
single-bit error occurs, the single-bit error counter register is incremented, its value compared to
the single-bit error trigger register. An error is reported when these values are equal. The