Freescale Semiconductor MSC8144E, Reference Manual

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Performance Monitor
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 25-73
Table 25-39. Performance Monitor Events Performance
Event Counted Number Description of Event Counted
General Events
Nothing Ref:0 Register counter holds current value
System cycles C0 CCB (DSP core subsystem) clock
cycles
L2 ICache Events
Hit in L2 ICache bank 1 in user mode Ref:10 -
Hit in L2 ICache bank 2 in user mode Ref:11 -
Miss in L2 ICache bank 1 in user mode C1:57 -
Miss in L2 ICache bank 2 in user mode C2:0 -
Prefetch hit in L2 ICache bank 1 in user mode C3:60 -
Prefetch hit in L2 ICache bank 2 in user mode C4:0 -
Hold cycles in L2 ICache bank 1 in user mode C5:56 -
Hold cycles in L2 ICache bank 2 in user mode C6:0 -
Thrash miss in L2 ICache bank 1 C7:57 miss which cause to line thrashing in L2
ICache
Thrash miss in L2 ICache bank 2 C8:0 miss which cause to line thrashing in L2
ICache
Hit in L2 ICache bank 1 in supervisor mode Ref:12 -
Hit in L2 ICache bank 2 in supervisor mode Ref:13 —
Hold cycles in L2 ICache bank 1 in supervisor mode C4:2 —
Hold cycles in L2 ICache bank 2 in supervisor mode C5:1 —
Miss in L2 ICache bank 1 in supervisor mode C3:2 —
Miss in L2 ICache bank 2 in supervisor mode C4:3 —
Prefetch hit in L2 ICache bank 1 in supervisor mode C7:0 —
Prefetch hit in L2 ICache bank 2 in supervisor mode C8:1 —
DMA Events
Asserted for every cycle DMA specific channel is active C5:2
Asserted for fourth cycles when DMA specific channel win
arbitration Ref:14 -
Asserted for one cycle when DMA finished buffer C6:1 —
C6:2
DMA specific channel request active in the system (Valid until get
address acknowledge) C7:1 -
Asserted for fourth cycles when DMA specific channel get
consecutive grant C8:2
-
RapidIO RMU EVENTS
Packet received of any priority C4:4
Packet received of priority 0 C2:3
Packet received of priority 1 C5:3