Freescale Semiconductor MSC8144E, Reference Manual

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Memory Management Unit (MMU)
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 10-3
10.2 Memory Management Unit (MMU)
The MMU provides a high-speed address translation mechanism to enable memory relocation,
and checks access permissions for core instructions and data buses. It also controls hardware task
protection and provides cache and bus controls for advanced memory management. The MMU
enables better integration of system resources and defines a cleaner software model. For example,
programming protected regions, address translation regions, cacheable regions, and so on can be
combined. In addition, cache usage can be optimized based on the specific attributes controlled
by the MMU programming. For memory protection, the MMU enables the implementation of an
RTOS with MMU support, thereby protecting the operating system, task code, and data from
errant tasks. Address translation enables implementation of a software model in which the code
uses virtual addresses that are translated to physical addresses accessing memory. The MMU
provides a virtual memory software model with a hole for the OCE and internal device registers
and peripherals. The core generates virtual addresses during its operation. The virtual address
together with the task ID from the MMU become the task-extended (TE) virtual address. The
MMU translates between virtual and physical addresses during each core access, providing
control attributes for each core access per memory segment, such as burst size, pre-fetch enable,
write-policy, cacheability, and so forth.
The MMU performs address translation on external (to the DSP core subsystem) addresses, from
virtual addresses (used by the software that runs on the core) to physical addresses (used by the
MBuses). Address translation is needed for several reasons, including:
„
Enabling the software to be written without consideration of the physical location of the
code in memory, thereby providing a simpler software model that enhances modularity
and re-use
„
Allowing true dynamic code relocation without any performance cost or overhead
The same virtual addresses can be re-used between tasks, with no need to flush the caches
between tasks. This is because the caches also store the task ID in their line tags, and thus have a
unique memory image per task. Protection and address translation are applied to memory
segments, defined in the MMU. A segment descriptor (SD) can be set (among other things) to
cacheable/non-cacheable, pre-fetch policy, shared/non-shared, and more. The MMU controls up
to 20 data and up to 12 program segment descriptors through the memory attributes and
translation table (MATT).
The MMU also handles all memory protection. If an attempted memory access is not permitted,
the MMU aborts the memory accesses by signalling the relevant DSP core subsystem
components via an MMU exception indication back to the core. The MMU also stores the
address and attributes of accesses that are not permitted. The MMU registers are
memory-mapped on the DQBus and are programmed using core move and bit-mask instructions.
Memory protection is required to increase the reliability of the system, so that errant tasks are not
allowed to ruin the privileged state and the state of other tasks. Program and data accesses from