Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
12-4 Freescale Semiconductor
DDR SDRAM Memory Controller
Figure 12-4 shows an example DDR SDRAM configuration with two physical banks, each
containing five 8 M
×
8 DDR modules for a total of 64 MB of system memory. One of the
modules is used for the memory ECC checking function. The AC timing specifications, desired
memory operating frequency, capacitive loads, and board routing loads can assist the system
designer in defining signal buffering requirements. The DDR memory controller drives 16
address pins, but in this example the DDR SDRAM devices use only 13 bits.
12.1.1 DDR SDRAM Interface Operation
The DDR memory controller supports many different DDR SDRAM configurations. Sixteen
multiplexed address signals and three logical bank select signals support device densities from
64 Mb to 4 Gb. The DDR SDRAM physical banks can be built from directly-attached memory
devices. The data path to individual physical banks is 32 or 16 bits wide (40 or 24 bits with ECC).
The DDR memory controller supports physical bank sizes from 16 MB to 1 GB. The physical
banks can be constructed using
×
8 or
×
16 DDR1 or DDR2 memory devices. Five data qualifier
(DQM including DQM for ECC) signals provide byte selection for memory accesses.
Note: An 8-bit DDR SDRAM device has a
DQM
signal and eight data signals (
DQ[0–7]
). A
16-bit DDR SDRAM device has two
DQM
signals associated with specific halves of the
16 data signals (
DQ[0–7]
and
DQ[8–15]
).