Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
26-16 Freescale Semiconductor
Security Engine (SEC)
— controller sends descriptor to channel over the internal bus
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Transferring a data length parameter from a channel to the EU
— channel makes request, arbitrates for attention from controller
— controller transfers data from channel to EU over the internal bus
„
Obtaining input data from external memory for input to an EU
— channel makes request, arbitrates for attention from controller
— controller arbitrates for use of the system bus and performs read from external memory
— controller sends data to EU over the internal bus. If insnooping, data is sent to two EUs
„
Writing output data from an EU back to external memory
— channel makes request, arbitrates for attention from controller
— controller begins reading data from the EU into a controller FIFO. If outsnooping, the
same data is also read by another EU. Meanwhile, the controller arbitrates for use of
the system bus.
— controller performs write to external memory
26.2.3.1 Arbitration for Use of the Controller and Buses
The controller attempts to maximize utilization of the system bus by grouping outstanding bus
requests from the channels by request type (read or write). The controller performs all write
requests to the system bus, followed by all read requests, and then repeats.
Within a request type, the controller grants bus access via the same snapshot scheme used for
granting EUs. If, for example, the controller is doing writes, it takes a snapshot of the current
write requests, satisfies them as the bus becomes available, then takes another snapshot of write
requests, and repeats. If there are no more write requests in a snapshot, the arbiter switches to
handling reads. It repeatedly takes snapshots of the reads waiting and satisfies them until there
are no more read requests in a snapshot. It then switches back to handling writes.
As with arbitration for EUs, controls for setting channel priorities for bus access are in the Master
Control Register (Section 26.5.4.1, Master Control Register (MCR)), and the same two
methods are available for selecting which request to satisfy within a snapshot. If both the channel
3 and channel 4 bus priority count fields are set to non-zero values, the arbiter implement the
weighted priority scheme (see Section 26.2.2.1, Weighted Priority Arbitration). If both are zero,
the arbitration will be round-robin (see Section 26.2.2.2, Round-Robin Arbitration). Setting only
one of the fields to a non-zero value results in unpredictable operation. When the buses are
granted to a channel, they are granted until the channel transfer is completely satisfied.
The SEC does not dynamically adjust its own transaction priorities. System software, however,
can adjust SEC transaction priority in real time, with the change in priority taking effect
immediately.