Freescale Semiconductor MSC8144E, Reference Manual

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Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 26-99
26.5.5.4 Channel Fetch FIFO (CFF)
Each channel contains a FIFO to store a queue of descriptor pointers starting with the address of
the first byte of descriptors to process. Typically, the core processor creates a descriptor in
memory containing all relevant mode and location information for the SEC and then launches the
descriptor by writing its address to the SEC Fetch FIFO. The Fetch FIFO can hold up to 24
descriptor pointers at a time. When the end of the current descriptor is reached, the descriptor
pointed to by the next location in the Fetch FIFO is read to launch the next descriptor. The Fetch
Address is written into the FIFO only if the write includes the least significant byte. If extended
addressing mode is selected (the EAE bit is high—see Table 26-18 for details), then the
Extended Fetch Address must be written before or concurrent with the Fetch Address. Specifying
a FETCH_ADRS of 0 causes the channel to generate an error and stop. The bits in the CFF
perform the functions described in Table 26-22.
CFF1 Channel Fetch FIFOs Offset 0xC1148
CFF2 Offset 0xC1248
CFF3 Offset 0xC1348
CFF4 Offset 0xC1448
Bits 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
Field —
Type W
Reset 0x0000
Bits 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Field — EPTR
Type W
Reset 0x0000
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field FETCH_ADR
Type W
Reset 0x0000
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field FETCH_ADR
Type W
Reset 0x0000
Table 26-23. CFF Bit Field Descriptions
Bits Reset Description
—
63–36
0 Reserved. Write to zero for future compatibility.
EPTR
35–32
0 Extended Pointer
Concatenated as the upper 4 bits of the fetch address when extended mode is selected (EAE is
high—see Table 26-18 for details).
FETCH_ADR
31–0
0 Fetch Address
Pointer to the memory location for the descriptor that the core processor wants the SEC to fetch.