Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
26-90 Freescale Semiconductor
Security Engine (SEC)
Table 26-18. CCR Bit Field Descriptions
Bits Reset Description Settings
—
63–34
0 Reserved. Write to zero for future compatibility.
CON
33
0 Continue
Used to perform a partial reset that does not clear the lower half
of the CCR or the Fetch FIFO. After the reset sequence
completes, this bit automatically clears (0) and the channel
resumes normal operation servicing the next descriptor pointer in
the Fetch FIFO, if any is present. 0 No special action.
1 Partial reset.
R
32
0 Reset Channel
Used to perform a soft reset of the channel. The details of the
software reset actions depend upon what the channel is doing
when the bit is set:
• If the R bit is set while the channel is requesting an EU
assignment from the controller, the channel cancels its request
by asserting the release output signals. The channel then
resets all its registers, clears the R bit, and returns the channel
state machine to the idle state.
• If the R bit is set after the channel is assigned to an EU, the
channel requests a write from the controller to set the software
reset bit of the EU. If a secondary EU has been reserved, the
channel requests a write to reset that EU as well. The channel
next asserts the appropriate release signal to notify the
controller that the channel has finished with the reserved EU(s).
The channel then resets all the registers, clears the R bit and
returns the channel state machine to the idle state.
0 No special action.
1 Initiates a soft reset of the
channel, clearing all of its
internal state.
—
31–9
0 Reserved. Write to zero for future compatibility.
BS
8
0 Burst Size
This bit determines the burst size used by the SEC to access long
text-data parcels in main memory. 0 Burst size is 64 bytes.
1 Burst size is 128 bytes.
IWSE
7
0 ICV Writeback Status Enable
If this bit is set and the descriptor calls for ICV comparison, then
at completion of descriptor processing, the channel writes back to
the descriptor header all the required writeback information:
DONE, ICCR0, and ICCR1 fields. 0 No special action.
1 Write back the required data
after processing if ICV
comparison is required.
—
6
0 Reserved. Write to zero for future compatibility.
EAE
5
0 Extend Address Enable
Selects whether to use 32-bit or 36-bit addressing. 0 Channel address bus is 32
bits.
1 Channel address bus is 36
bits.
CDWE
4
0 Channel Done Writeback Enable
Enables/disables writeback of the DONE field after descriptor
processing is completed if the NT or DN bit is set in the descriptor
header. When enabled, the core processor can poll the memory
location of the original descriptor to determine if the processing
for that descriptor is completed. 0 Channel Done writeback
disabled.
1 Channel Done writeback
enabled.
AWSE
3
0 Always Writeback Status Enable
When set, enables the channel after completing descriptor
processing to writeback all the writeback information: DONE,
ICCR0, and ICCR1 fields. When set, this field overrides IWSE,
which then has no effect. 0 No special action.
1 Always writeback DONE,
ICCR0, and ICCR1 fields
after descriptor processing.