NXP Semiconductors LCP43 Series, User Manual

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User manual Rev. 1.3 — 6 July 2012 472 of 1269
NXP Semiconductors
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Chapter 21: LPC43xx External Memory Controller (EMC)
DYNAMICRASCAS3 R/W 0x164 Selects the RAS and CAS latencies for
dynamic memory chip select 3. 0x303 0x303 Table 374
- - 0x168 -
0x1FC Reserved. - - -
STATICCONFIG0 R/W 0x200 Selects the memory configuration for
static chip select 0. 0 0x81 Table 375
STATICWAITWEN0 R/W 0x204 Selects the delay from chip select 0 to
write enable. 0 0 Table 376
STATICWAITOEN0 R/W 0x208 Selects the delay from chip select 0 or
address change, whichever is later, to
output enable. 0 0 Table 377
STATICWAITRD0 R/W 0x20C Selects the delay from chip select 0 to a
read access. 0x1F
[2]
0xE Table 378
STATICWAITPAGE0 R/W 0x210 Selects the delay for asynchronous page
mode sequential accesses for chip
select 0. 0x1F 0x1F Table 379
STATICWAITWR0 R/W 0x214 Selects the delay from chip select 0 to a
write access. 0x1F 0x1F Table 380
STATICWAITTURN0 R/W 0x218 Selects the number of bus turnaround
cycles for chip select 0. 0xF 0xF Table 381
- - 0x21C Reserved. - - -
STATICCONFIG1 R/W 0x220 Selects the memory configuration for
static chip select 1. 0 0 Table 375
STATICWAITWEN1 R/W 0x224 Selects the delay from chip select 1 to
write enable. 0 0 Table 376
STATICWAITOEN1 R/W 0x228 Selects the delay from chip select 1 or
address change, whichever is later, to
output enable. 0 0 Table 377
STATICWAITRD1 R/W 0x22C Selects the delay from chip select 1 to a
read access. 0x1F 0x1F Table 378
STATICWAITPAGE1 R/W 0x230 Selects the delay for asynchronous page
mode sequential accesses for chip
select 1. 0x1F 0x1F Table 379
STATICWAITWR1 R/W 0x234 Selects the delay from chip select 1 to a
write access. 0x1F 0x1F Table 380
STATICWAITTURN1 R/W 0x238 Selects the number of bus turnaround
cycles for chip select 1. 0xF 0xF Table 381
- - 0x23C Reserved. - - -
STATICCONFIG2 R/W 0x240 Selects the memory configuration for
static chip select 2. 0 0 Table 375
STATICWAITWEN2 R/W 0x244 Selects the delay from chip select 2 to
write enable. 0 0 Table 376
Table 353. Register overview: External memory controller (base address 0x4000 5000)
…continued
Name Access Address
offset
Description Reset
value Reset
value
after
EMC
boot Reference