UM10503
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User manual
Rev. 1.3 — 6 July 2012
491 of 1269
NXP Semiconductors
UM10503
Chapter 21: LPC43xx External Memory Controller (EMC)
Bus turn-around cycles are generated between external bus transfers in the following
situations when at least one of the memory banks is static memory:
•
between read and read to different memory banks
•
between read and write to the same memory bank
•
between read and write to different memory banks
Bus turn-around cycles prevent bus contention on the external memory data bus.
Table 381. Static Memory Turn Round Delay registers (STATICWAITTURN[0:3], address
0x4000 5218 (STATICWAITTURN0), 0x4000 5238 (STATICWAITTURN1),
0x4000 5258 (STATICWAITTURN2), 0x4000 5278 (STATICWAITTURN3)) bit
description
Bit
Symbol
Description
Reset
value
3:0
WAITTURN Bus turnaround cycles.
0x0 - 0xE = (n + 1) CCLK turnaround cycles. Bus turnaround time is
(WA 1) x tCCLK.
0xF = 16 CCLK turnaround cycles (POR reset value).
0xF
31:4
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
-
