UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
357 of 1269
NXP Semiconductors
UM10503
Chapter 18: LPC43xx Serial GPIO (SGPIO)
18.6.3 Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15)
Each register controls a slice multiplexer shift clock and how many bits of the slice FIFO
are shifted per clock.
Registers SLICE_MUX_CFG0 to SLICE_MUX_CFG15 control slices A (register 0) to P
(register 15).
Bit MATCH_MODE selects whether the match filter is active or whether data is captured.
Only slice A, H, I, and P support matching with a mask (register MASK_x). For other slices
the pattern is not masked.
Bit CLKGEN_MODE selects as shift clock the clock generated by the slice counter or by
an external pin or other slice.
Bit INV_OUT_CLK can invert the shift clock. This should only be used for external clocks
coming from a pin.
Data_capture_mode is used to define which input data condition can generate an
interrupt.
See
for connecting slice data to pins for the various setting of bits
PARALLEL_MODE.
Table 216. SGPIO multiplexer
slice
Slice Din
slice
Clock
Slice Din
CONCAT_ENABLE
CLK_SOURCE_ SLICE_MODE
0
1
CONCAT_ORDER
00
01
10
11
00
01
10
11
A
Pin 0
A
I
J
L
A
D
H
O
P
I
Pin 1
I
A
A
A
I
D
H
O
P
E
Pin 2
E
J
I
I
E
D
H
O
P
J
Pin 3
J
E
E
E
J
D
H
O
P
C
Pin 4
C
K
L
J
C
D
H
O
P
K
Pin 5
K
C
C
C
K
D
H
O
P
F
Pin6
F
L
K
K
F
D
H
O
P
L
Pin 7
L
F
F
F
L
D
H
O
P
B
Pin 8
B
M
N
P
B
D
H
O
P
M
Pin 9
M
B
B
B
M
D
H
O
P
G
Pin 10
G
N
M
M
G
D
H
O
P
N
Pin 11
N
G
G
G
N
D
H
O
P
D
Pin 12
D
O
P
N
D
-
-
-
-
O
Pin13
O
D
D
D
O
-
-
-
-
H
Pin 14
H
P
O
O
H
-
-
-
-
P
Pin15
P
H
H
H
P
-
-
-
-
