UM10503
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User manual
Rev. 1.3 — 6 July 2012
759 of 1269
NXP Semiconductors
UM10503
Chapter 26: LPC43xx Ethernet
Table 591. Receive descriptor fields 1 (RDES1)
Bit
Symbol
Description
12:0
RBS1
Receive Buffer 1 Size
Indicates the first data buffer size in bytes. The buffer size must be a multiple
of 4, 8, or 16, depending upon the bus widths (32, 64, or 128), even if the
value of RDES2 (buffer1 address pointer) is not aligned. When the buffer
size is not a multiple of 4, 8, or 16, the resulting behavior is undefined. If this
field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor
depending on the value of RCH (Bit 14). See
for further
details on calculating buffer sizes.
13
-
Reserved
14
RCH
Second Address Chained
When set, this bit indicates that the second address in the descriptor is the
Next Descriptor address rather than the second buffer address. When this
bit is set, RBS2 (RDES1[28:16]) is a “don’t care” value. RDES1[15] takes
precedence over RDES1[14].
15
RER
Receive End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor.
The DMA returns to the base address of the list, creating a descriptor ring.
28:16
RBS2
Receive Buffer 2 Size
These bits indicate the second data buffer size, in bytes. The buffer size
must be a multiple of 4, even if the value of RDES3 (buffer2 address pointer)
is not aligned to bus width. If the buffer size is not an appropriate multiple of
4, the resulting behavior is undefined. This field is not valid if RDES1[14] is
set. See
for further details on calculating buffer sizes.
Table 592. Receive descriptor fields 2 (RDES2)
Bit
Symbol
Description
31:0
B1ADD
Address Pointer
These bits indicate the physical address of Buffer 1. There are no limitations
on the buffer address alignment except for the following condition: The DMA
uses the configured value for its address generation when the RDES2 value
is used to store the start of frame. Note that the DMA performs a write
operation with the RDES20 bits as 0 during the transfer of the start of frame
but the frame data is shifted as per the actual Buffer address pointer. The
DMA ignores RDES20 if the address pointer is to a buffer where the middle
or last part of the frame is stored. See
for further details on
buffer address alignment.
Table 593. Receive descriptor fields 3 (RDES3)
Bit
Symbol
Description
31:0
B2ADD
Buffer 2 Address Pointer (Next Descriptor Address)
These bits indicate the physical address of Buffer 2 when a descriptor ring
structure is used. If the Second Address Chained (RDES1[24]) bit is set, this
address contains the pointer to the physical memory where the Next
Descriptor is present. If RDES1[24] is set, the buffer (Next Descriptor)
address pointer must be bus width-aligned (RDES3[1:0] = 0. LSBs are
ignored internally.) However, when RDES1[24] is reset, there are no
limitations on the RDES3 value, except for the following condition: The DMA
uses the configured value for its buffer address generation when the RDES3
value is used to store the start of frame. The DMA ignores RDES3 [1:0] if the
address pointer is to a buffer where the middle or last part of the frame is
stored.
