UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
494 of 1269
NXP Semiconductors
UM10503
Chapter 21: LPC43xx External Memory Controller (EMC)
•
Buffer read requests from memory. Future read requests that hit the buffer read the
data from the buffer rather than memory, reducing transaction latency.
Convert all read transactions into quadword bursts on the external memory interface.
This enhances transfer efficiency for dynamic memory.
•
Reduce external memory traffic. This improves memory bandwidth and reduces
power consumption.
Read buffer operation:
•
If the buffers are enabled and the read data is contained in one of the buffers, the read
data is provided directly from the buffer.
•
If the read data is not contained in a buffer, the LRU buffer is selected. If the buffer is
dirty (contains write data), the write data is flushed to memory. When an empty buffer
is available the read command is posted to the memory.
A buffer filled by performing a read from memory is marked as not-dirty (not containing
write data) and its contents are not flushed back to the memory controller unless a
subsequent AHB transfer performs a write that hits the buffer.
21.8.5 Using the EMC with SDRAM
21.8.5.1 SDRAM burst length
For 32-bit wide chip selects data is transferred to and from dynamic memory in SDRAM
bursts of four. For 16-bit wide chip selects SDRAM bursts of eight are used.
21.8.5.2 SDRAM mode register burst length set-up
To be used with the EMC, the SDRAM must be configured for a 128-bit sequential burst.
The burst length is configured through the mode register in the SDRAM memory. The
layout for a JEDEC standard SDRAM mode register is shown in
. The EMC
address bits are mapped to the SDRAM mode register bits as indicated in
