NXP Semiconductors LCP43 Series, User Manual

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User manual Rev. 1.3 — 6 July 2012 1216 of 1269
NXP Semiconductors
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Chapter 49: LPC43xx ARM Cortex M0/M4 reference
[1] Division operations use early termination to minimize the number of cycles required based on the number
of leading ones and zeroes in the input operands.
[2] Neighboring load and store single instructions can pipeline their address and data phases. This enables
these instructions to complete in a single execution cycle.
[3] Conditional branch completes in a single cycle if the branch is not taken.
Branch Conditional B<cc> <label> 1 or 1 + P
[3]
Unconditional B <label> 1 + P
With link BL <label> 1 + P
With exchange BX Rm 1 + P
With link and exchange BLX Rm 1 + P
Branch if zero CBZ Rn, <label> 1 or 1 + P
[3]
Branch if non-zero CBNZ Rn, <label> 1 or 1 + P
[3]
Byte table branch TBB [Rn, Rm] 2 + P
Halfword table branch TBH [Rn, Rm, LSL#1] 2 + P
State change Supervisor call SVC
#<imm>
If-then-else IT... <cond> 1
[4]
Disable interrupts CPSID <flags> 1 or 2
Enable interrupts CPSIE <flags> 1 or 2
Read special register MRS Rd, <specreg> 1 or 2
Write special register MSR <specreg>, Rn 1 or 2
Breakpoint BKPT #<imm> -
Extend Signed halfword to word SXTH Rd, <op2> 1
Signed byte to word SXTB Rd, <op2> 1
Unsigned halfword UXTH Rd, <op2> 1
Unsigned byte UXTB Rd, <op2> 1
Bit field Extract unsigned UBFX Rd, Rn, #<imm>, #<imm> 1
Extract signed SBFX Rd, Rn, #<imm>, #<imm> 1
Clear BFC Rd, Rn, #<imm>, #<imm> 1
Insert BFI Rd, Rn, #<imm>, #<imm> 1
Reverse Bytes in word REV Rd, Rm 1
Bytes in both halfwords REV16 Rd, Rm 1
Signed bottom halfword REVSH Rd, Rm 1
Bits in word RBIT Rd, Rm 1
Hint Send event SEV 1
Wait for event WFE 1 + W
Wait for interrupt WFI 1 + W
No operation NOP 1
Barriers Instruction synchronization ISB 1 + B
Data memory DMB 1 + B
Data synchronization DSB <flags> 1 + B
Table 1083.Cortex-M4 instruction set summary
Operation Description Assembler Cycles