UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
402 of 1269
NXP Semiconductors
UM10503
Chapter 19: LPC43xx General Purpose DMA (GPDMA) controller
19.7 Functional description
19.7.1 DMA controller functional description
The DMA Controller enables peripheral-to-memory, memory-to-peripheral,
peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream
provides unidirectional serial DMA transfers for a single source and destination. For
example, a bidirectional port requires one stream for transmit and one for receive. The
source and destination areas can each be either a memory region or a peripheral, and
can be accessed through the AHB master.
shows a block diagram of the DMA
Controller.
The functions of the DMA Controller are described in the following sections.
19.7.1.1 AHB slave interface
All transactions to DMA Controller registers on the AHB slave interface are 32 bits wide.
Eight bit and 16-bit accesses are not supported and will result in an exception.
19.7.1.2 Control logic and register bank
The register block stores data written or to be read across the AHB interface.
19.7.1.3 DMA request and response interface
See DMA Interface description for information on the DMA request and response
interface.
19.7.1.4 Channel logic and channel register bank
The channel logic and channel register bank contains registers and logic required for each
DMA channel.
19.7.1.5 Interrupt request
The interrupt request generates the interrupt to the ARM processor.
19.7.1.6 AHB master interface
The DMA Controller contains two AHB master interfaces. Each AHB master is capable of
dealing with all types of AHB transactions, including:
•
Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the DMA Controller stalls and waits until the transaction can complete.
•
Locked transfers for source and destination of each stream.
•
Setting of protection bits for transfers on each stream.
19.7.1.6.1
Bus and transfer widths
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths and can be the same width or narrower than the physical bus width. The
DMA Controller packs or unpacks data as appropriate.
19.7.1.6.2
Endian behavior
The DMA Controller can cope with both little-endian and big-endian addressing. Software
can set the endianness of each AHB master individually.
