NXP Semiconductors LCP43 Series, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 1215 of 1269
NXP Semiconductors
UM10503
Chapter 49: LPC43xx ARM Cortex M0/M4 reference
Load Word LDR Rd, [Rn, <op2>] 2
[2]
To PC LDR PC, [Rn, <op2>] 2
[2]
+ P
Halfword LDRH Rd, [Rn, <op2>] 2
[2]
Byte LDRB Rd, [Rn, <op2>] 2
[2]
Signed halfword LDRSH Rd, [Rn, <op2>] 2
[2]
Signed byte LDRSB Rd, [Rn, <op2>] 2
[2]
User word LDRT Rd, [Rn, #<imm>] 2
[2]
User halfword LDRHT Rd, [Rn, #<imm>] 2
[2]
User byte LDRBT Rd, [Rn, #<imm>] 2
[2]
User signed halfword LDRSHT Rd, [Rn, #<imm>] 2
[2]
User signed byte LDRSBT Rd, [Rn, #<imm>] 2
[2]
PC relative LDR Rd,[PC, #<imm>] 2
[2]
Doubleword LDRD Rd, Rd, [Rn, #<imm>] 1 + N
Multiple LDM Rn, {<reglist>} 1 + N
Multiple including PC LDM Rn, {<reglist>, PC} 1 + N + P
Store Word STR Rd, [Rn, <op2>] 2
[2]
Halfword STRH Rd, [Rn, <op2>] 2
[2]
Byte STRB Rd, [Rn, <op2>] 2
[2]
Signed halfword STRSH Rd, [Rn, <op2>] 2
[2]
Signed byte STRSB Rd, [Rn, <op2>] 2
[2]
User word STRT Rd, [Rn, #<imm>] 2
[2]
User halfword STRHT Rd, [Rn, #<imm>] 2
[2]
User byte STRBT Rd, [Rn, #<imm>] 2
[2]
User signed halfword STRSHT Rd, [Rn, #<imm>] 2
[2]
User signed byte STRSBT Rd, [Rn, #<imm>] 2
[2]
Doubleword STRD Rd, Rd, [Rn, #<imm>] 1 + N
Multiple STM Rn, {<reglist>} 1 + N
Push Push PUSH {<reglist>} 1 + N
Push with link register PUSH {<reglist>, LR} 1 + N
Pop Pop POP {<reglist>} 1 + N
Pop and return POP {<reglist>, PC} 1 + N + P
Semaphore Load exclusive LDREX Rd, [Rn, #<imm>] 2
Load exclusive half LDREXH Rd, [Rn] 2
Load exclusive byte LDREXB Rd, [Rn] 2
Store exclusive STREX Rd, Rt, [Rn, #<imm>] 2
Store exclusive half STREXH Rd, Rt, [Rn] 2
Store exclusive byte STREXB Rd, Rt, [Rn] 2
Clear exclusive monitor CLREX 1
Table 1083.Cortex-M4 instruction set summary
Operation Description Assembler Cycles