UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
1061 of 1269
42.1 How to read this chapter
The C_CAN0/1 controllers are available on all LPC43xx parts.
42.2 Basic configuration
The C_CAN is configured as follows:
•
See
for clocking and power control.
•
The C_CAN0 is reset by the CAN0_RST (reset # 55).
•
The C_CAN1 is reset by the CAN1_RST (reset # 56).
•
The ORed C_CAN0 and C_CAN1 interrupt is connected to slot # 12 in the Event
router.
•
The C_CAN0 interrupt is connected to interrupt #51 in the NVIC.
•
The C_CAN1 interrupt is connected to interrupt #43 in the NVIC.
Remark:
The clocks to the C_CAN0 and C_CAN1 interfaces can be set independently of
each other.
42.3 Features
•
Conforms to protocol version 2.0 parts A and B.
•
Supports bit rate of up to 1 Mbit/s.
•
Supports 32 Message Objects.
•
Each Message Object has its own identifier mask.
•
Provides programmable FIFO mode (concatenation of Message Objects).
•
Provides maskable interrupts.
•
Supports Disabled Automatic Retransmission (DAR) mode for time-triggered CAN
applications.
•
Provides programmable loop-back mode for self-test operation.
UM10503
Chapter 42: LPC43xx C_CAN
Rev. 1.3 — 6 July 2012
User manual
Table 929. C_CAN clocking and power control
Base clock
Branch clock
Operating
frequency
Clock to the C_CAN0 register interface
and C_CAN0 peripheral clock (PCLK).
BASE_APB3_CLK
CLK_APB3_CAN0
up to
204 MHz
Clock to the C_CAN1 register interface
and C_CAN1 peripheral clock (PCLK).
BASE_APB1_CLK
CLK_APB1_CAN1
up to
204 MHz
