NXP Semiconductors LCP43 Series, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 550 of 1269
NXP Semiconductors
UM10503
Chapter 23: LPC43xx USB0 Host/Device/OTG controller
block in the system, the transaction translator function normally associated with a high
speed hub has been implemented within the DMA and Protocol engine blocks. The
embedded transaction translator function is an extension to EHCI interface but
makes use of the standard data structures and operational models that exist in the EHCI
specification to support full and low speed devices.
23.8.1.1 Capability registers
The following items have been added to the capability registers to support the embedded
Transaction Translator Function:
•
N_TT bits added to HCSPARAMS – Host Control Structural Parameters (see
Table 395 ).
•
N_PTT added to HCSPARAMS – Host Control Structural Parameters (see Table 395 ).
23.8.1.2 Operational registers
The following items have been added to the operational registers to support the
embedded TT:
•
New register TTCTRL (see Section 23.6.9 ).
•
Two-bit Port Speed (PSPD) bits added to the PORTSC1 register (see
Section 23.6.15 ).
23.8.1.3 Discovery
In a standard EHCI controller design, the EHCI host controller driver detects a Full speed
(FS) or Low speed (LS) device by noting if the port enable bit is set after the port reset
operation. The port enable will only be set in a standard EHCI controller implementation
after the port reset operation and when the host and device negotiate a High-Speed
connection (i.e. Chirp completes successfully). Since this controller has an embedded
Transaction Translator, the port enable will always be set after the port reset operation
regardless of the result of the host device chirp result and the resulting port speed will be
indicated by the PSPD field in PORTSC1 (see
Section 23.6.15 ).
Table 432. Handling of directly connected full-speed and low-speed devices
Standard EHCI model EHCI with embedded Transaction Translator
After the port enable bit is set following a
connection and reset sequence, the device/hub
is assumed to be HS. After the port enable bit is set following a
connection and reset sequence, the device/hub
speed is noted from PORTSC1.
FS and LS devices are assumed to be
downstream from a HS hub thus, all port-level
control is performed through the Hub Class to
the nearest Hub. FS and LS device can be either downstream
from a HS hub or directly attached. When the
FS/LS device is downstream from a HS hub,
then port-level control is done using the Hub
Class through the nearest Hub. When a FS/LS
device is directly attached, then port-level
control is accomplished using PORTSC1.
FS and LS devices are assumed to be
downstream from a HS hub with HubAddr=X,
where HubAddr > 0 and HubAddr is the address
of the Hub where the bus transitions from HS to
FS/LS (i.e. Split target hub). FS and LS device can be either downstream
from a HS hub with HubAddr = X [HubAddr > 0]
or directly attached, where HubAddr = TTHA
(TTHA is programmable and defaults to 0) and
HubAddr is the address of the Root Hub where
the bus transitions from HS to FS/LS (i.e. Split
target hub is the root hub).