NXP Semiconductors LCP43 Series, User Manual

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User manual Rev. 1.3 — 6 July 2012 470 of 1269
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Chapter 21: LPC43xx External Memory Controller (EMC)
21.6 Pin description
21.7 Register description
This chapter describes the EMC registers and provides details required when
programming the microcontroller. The EMC registers are shown in
Table 353 .
Reset value reflects the data stored in used bits only. It does not include the content of
reserved bits.
Table 352. EMC pin description
Pin function Direction Description
EMC_A[22:0] O Address bus
EMC_D[31:0] I/O Data bus
EMC_BLS[3:0] O Byte lane select
EMC_CS[3:0] O Static RAM memory bank select
EMC_OE O Output enable
EMC_WE O Write enable
EMC_CKEOUT[3:0] O SDRAM clock enable signals
EMC_CLK[3:0];
EMC_CLK01;
EMC_CLK23 O SDRAM clock signals
EMC_DQMOUT[3:0] O Data mask output to SDRAM memory banks
EMC_DYCS[3:0] O SDRAM memory bank select
EMC_CAS O Column address strobe
EMC_RAS O Row address strobe
Table 353. Register overview: External memory controller (base address 0x4000 5000)
Name Access Address
offset
Description Reset
value Reset
value
after
EMC
boot Reference
CONTROL R/W 0x000 Controls operation of the memory
controller. 0x3
[1]
0x1 Table 354
STATUS RO 0x004 Provides EMC status information. 0x5 0x5 Table 355
CONFIG R/W 0x008 Configures operation of the memory
controller. 0 0 Table 356
- - 0x00C -
0x01C Reserved. - - -
DYNAMICCONTROL R/W 0x020 Controls dynamic memory operation. 0x6 0x6 Table 357
DYNAMICREFRESH R/W 0x024 Configures dynamic memory refresh
operation. 0 0 Table 358
DYNAMICREADCONFIG R/W 0x028 Configures the dynamic memory read
strategy. 0 0 Table 359
- - 0x02C Reserved. - - -
DYNAMICRP R/W 0x030 Selects the precharge command period. 0xF 0xF Table 360