NXP Semiconductors LCP43 Series, User Manual

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User manual Rev. 1.3 — 6 July 2012 473 of 1269
NXP Semiconductors
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Chapter 21: LPC43xx External Memory Controller (EMC)
[1] The reset value after warm reset for the CONTROL register is 0x0000 0001.
[2] If booting from EMC, see Section 5.3.5.2 .
21.7.1 EMC Control register
The Control register is a read/write register that controls operation of the memory
controller. The control bits can be altered during normal operation.
STATICWAITOEN2 R/W 0x248 Selects the delay from chip select 2 or
address change, whichever is later, to
output enable. 0 0 Table 377
STATICWAITRD2 R/W 0x24C Selects the delay from chip select 2 to a
read access. 0x1F 0x1F Table 378
STATICWAITPAGE2 R/W 0x250 Selects the delay for asynchronous page
mode sequential accesses for chip
select 2. 0x1F 0x1F Table 379
STATICWAITWR2 R/W 0x254 Selects the delay from chip select 2 to a
write access. 0x1F 0x1F Table 380
STATICWAITTURN2 R/W 0x258 Selects the number of bus turnaround
cycles for chip select 2. 0xF 0xF Table 381
- - 0x25C Reserved. - - -
STATICCONFIG3 R/W 0x260 Selects the memory configuration for
static chip select 3. 0 0 Table 375
STATICWAITWEN3 R/W 0x264 Selects the delay from chip select 3 to
write enable. 0 0 Table 376
STATICWAITOEN3 R/W 0x268 Selects the delay from chip select 3 or
address change, whichever is later, to
output enable. 0 0 Table 377
STATICWAITRD3 R/W 0x26C Selects the delay from chip select 3 to a
read access. 0x1F 0x1F Table 378
STATICWAITPAGE3 R/W 0x270 Selects the delay for asynchronous page
mode sequential accesses for chip
select 3. 0x1F 0x1F Table 379
STATICWAITWR3 R/W 0x274 Selects the delay from chip select 3 to a
write access. 0x1F 0x1F Table 380
STATICWAITTURN3 R/W 0x278 Selects the number of bus turnaround
cycles for chip select 3. 0xF 0xF Table 381
Table 353. Register overview: External memory controller (base address 0x4000 5000)
…continued
Name Access Address
offset
Description Reset
value Reset
value
after
EMC
boot Reference