UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
526 of 1269
NXP Semiconductors
UM10503
Chapter 23: LPC43xx USB0 Host/Device/OTG controller
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller
checks to ensure T
p
remains before the end of the (micro) frame. If so it proceeds to
pre-fill the TX FIFO. If at anytime during the pre-fill operation the time remaining the
[micro]frame is < T
s
then the packet attempt ceases and the packet is tried at a later time.
Although this is not an error condition and the host controller will eventually recover, a
mark will be made the scheduler health counter to note the occurrence of a “backoff”
event. When a back-off event is detected, the partial packet fetched may need to be
discarded from the latency buffer to make room for periodic traffic that will begin after the
next SOF. Too many back-off events can waste bandwidth and power on the system bus
and thus should be minimized (not necessarily eliminated). Backoffs can be minimized
with use of the TSCHHEALTH (T
ff
) described below.
23.6.12 BINTERVAL register
This register defines the bInterval value which determines the length of the virtual frame
(see
). The BINTERVAL register divides the SOF signal by the value BINT.
Remark:
The BINTERVAL register is not related to the bInterval endpoint descriptor field
in the USB specification.
Table 415. USB Transfer buffer Fill Tuning register in host mode (TXFILLTUNING - address 0x4000 6164) bit
description
Bit
Symbol
Description
Reset
value
Access
7:0
TXSCHOH
FIFO burst threshold
This register controls the number of data bursts that are posted to the TX
latency FIFO in host mode before the packet begins on to the bus. The
minimum value is 2 and this value should be a low as possible to maximize
USB performance. A higher value can be used in systems with unpredictable
latency and/or insufficient bandwidth where the FIFO may underrun because
the data transferred from the latency FIFO to USB occurs before it can be
replenished from system memory. This value is ignored if the Stream Disable
bit in USBMODE register is set.
0x2
R/W
12:8
TXSCHEATLTH
Scheduler health counter
This register increments when the host controller fails to fill the TX latency
FIFO to the level programmed by TXFIFOTHRES before running out of time
to send the packet before the next Start-Of-Frame .
This health counter measures the number of times this occurs to provide
feedback to selecting a proper TXSCHOH. Writing to this register will clear the
counter. The maximum value is 31.
0x0
R/W
15:13
-
Reserved
-
-
21:16
TXFIFOTHRES
Scheduler overhead
This register adds an additional fixed offset to the schedule time estimator
described above as T
ff
. As an approximation, the value chosen for this register
should limit the number of back-off events captured in the TXSCHHEALTH to
less than 10 per second in a highly utilized bus. Choosing a value that is too
high for this register is not desired as it can needlessly reduce USB utilization.
The time unit represented in this register is 1.267
s when a device is
connected in High-Speed Mode for OTG and SPH.
The time unit represented in this register is 6.333
s when a device is
connected in Low/Full Speed Mode for OTG and SPH.
0x0
R/W
31:22
-
Reserved
