UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
911 of 1269
32.1 How to read this chapter
The RIT is available on all LPC43xx parts.
32.2 Basic configuration
The RIT is configured as follows:
•
See
for clocking and power control.
•
The RIT is reset by the RITIMER_RST (reset #36).
•
The RIT interrupt is connected to slot # 11 in the NVIC.
32.3 Features
•
32-bit counter running from BASE_M4_CLK. Counter can be free-running, or be reset
by a generated interrupt.
•
32-bit compare value.
•
32-bit compare mask. An interrupt is generated when the counter value equals the
compare value after masking. This allows for combinations not possible with a simple
compare.
32.4 General description
The Repetitive Interrupt Timer (RIT) provides a versatile means of generating interrupts at
specified time intervals, without using a standard timer. It is intended for repeating
interrupts that aren’t related to Operating System interrupts. The RIT could also be used
as an alternative to the Cortex-M4 System Tick Timer if there are different system
requirements.
UM10503
Chapter 32: LPC43xx Repetitive Interrupt Timer (RIT)
Rev. 1.3 — 6 July 2012
User manual
Table 755. RIT clocking and power control
Base clock
Branch clock
Operating
frequency
Clock to the RI timer register interface and
RI timer peripheral clock (PCLK).
BASE_M4_CLK
CLK_M4_RITIMER
up to
204 MHz
