NXP Semiconductors LCP43 Series, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 812 of 1269
NXP Semiconductors
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Chapter 28: LPC43xx State Configurable Timer (SCT)
28.6 Register description
The register addresses of the State Configurable Timer are shown in Table 646 . For most
of the SCT registers, the register function depends on the setting of certain other register
bits:
1. The UNIFY bit in the CONFIG register determines whether the SCT is used as one
32-bit register (for operation as one 32-bit counter/timer) or as two 16-bit
counter/timers named L and H. The setting of the UNIFY bit is reflected in the register
map:
– UNIFY = 1: Only one register is used (for operation as one 32-bit counter/timer).
– UNIFY = 0: Access the L and H registers by a 32-bit read or write operation or can
be read or written to individually (for operation as two 16-bit counter/timers).
Typically, the UNIFY bit is configured by writing to the CONFIG register before any
other registers are accessed.
SCT output 8 ORed with Timer2 match output 0 CTOUT_8 ADC start1 input (ADC
CR register bit START =
0x3)
- 0
SCT output 8 CTOUT_8 ADC start1 input (ADC
CR register bit START =
0x3)
1
SCT output 9 ORed with Timer3 match output 3 CTOUT_9 - - 0
SCT output 9 CTOUT_9 - 1
SCT output 10 ORed with Timer3 match output 3 CTOUT_10 - - 0
SCT output 10 CTOUT_10 - 1
SCT output 11 ORed with Timer2 match output 3 CTOUT_11 T3 capture channel 3 - 0
SCT output 11 CTOUT_11 T3 capture channel 3 - 1
SCT output 12 ORed with Timer3 match output 3 CTOUT_12 - - 0
SCT output 12 CTOUT_12 - - 1
SCT output 13 ORed with Timer3 match output 3 CTOUT_13 - - 0
SCT output 13 CTOUT_13 - - 1
SCT output 14 ORed with Timer3 match output 2 CTOUT_14 Event router input 16 - 0
SCT output 14 CTOUT_14 Event router input 16 - 1
SCT output 15 ORed with Timer3 match output 3 CTOUT_15 T0 capture channel
3/ADC start0 input (ADC
CR register START bits
= 0x2)
- 0
SCT output 15 CTOUT_15 T0 capture channel
3/ADC start0 input (ADC
CR register START bits
= 0x2)
- 1
Table 645. SCT inputs and outputs
…continued
Description Pin function Internal signal Default (see
GIMA,
Table 148 )
CTOUTCTRL
bit (see
Table 50 )