NXP Semiconductors LCP43 Series, User Manual

Page: 95 / 1269

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 95 of 1269
NXP Semiconductors
UM10503
Chapter 11: LPC43xx Clock Generation Unit (CGU)
11.2.1.1 Changing the BASE_M4_CLK after power-up, reset, or deep power-down
mode
The following procedure shows how to change the default setting of the core clock
(BASE_M4_CLK = 96 MHz; IRC = clock source) to an operating frequency above
110 MHz while also changing the clock source from IRC to crystal oscillator:
1. Enable the crystal oscillator (see Table 69 ).
2. Wait 100

s.
3. Reconfigure PLL1 as follows (see Table 80 ):
– Select the M and N divider values to produce a PLL1 output > 110 MHz.
– Select the crystal oscillator as clock source for PLL1.
4. Wait for the PLL1 to lock.
The BASE_M4_CLK now operates in the high frequency range.
11.2.1.2 Changing the BASE_M4_CLK after waking up from deep-sleep or
power-down modes
The following procedure shows how to ramp up the BASE_M4_CLK clock from low
frequencies to the high frequency range (see
Figure 24 ). This procedure applies after
waking up from deep-sleep or power-down modes and any time the part runs at
frequencies < 90 MHz.
1. If the crystal oscillator is powered down, enable the crystal oscillator (see Table 69 ),
and wait 100

s.
2. Select the crystal oscillator as clock source for BASE_M4_CLK (see Table 88 ).
3. Reconfigure PLL1 as follows (see Table 80 ):
– Select the M and N divider values to produce a PLL1 output between 90 MHz and
110 MHz.
– Select the crystal oscillator as clock source for PLL1.
4. Wait for the PLL1 to lock.
5. Select the PLL1 output as clock source for BASE_CLK_M4.
The BASE_M4_CLK now operates in the mid-level frequency range.
To increase the frequency from mid-level to high operating frequencies above 110
MHz, continue as follows:
6. While the PLL1 is running, reconfigure the M and N dividers to produce a PLL1 output
> 110 MHz. Keep the crystal oscillator as the PLL1 clock source.
7. Wait for the PLL1 to lock.
The BASE_M4_CLK now operates in the high frequency range (110 MHz to 204 MHz).