UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
762 of 1269
27.1 How to read this chapter
The LCD controller is available on part LPC4350.
27.2 Basic configuration
The LCD controller is configured as follows:
•
See
for clocking and power control.
•
The LCD is reset by the LCD_RST (reset # 16).
•
The LCD interrupt is connected to interrupt slot # 7 in the NVIC.
27.3 Features
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AHB bus master interface to access frame buffer.
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Setup and control via a separate AHB slave interface.
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Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data.
•
Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays
with 4 or 8-bit interfaces.
•
Supports single and dual-panel color STN displays.
•
Supports Thin Film Transistor (TFT) color displays.
•
Programmable display resolution including, but not limited to: 320x200, 320x240,
640x200, 640x240, 640x480, 800x600, and 1024x768.
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Hardware cursor support for single-panel displays.
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15 gray-level monochrome, 3375 color STN, and 32K color palettized TFT support.
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1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.
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1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.
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16 bpp true-color non-palettized, for color STN and TFT.
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24 bpp true-color non-palettized, for color TFT.
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Programmable timing for different display panels.
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256 entry, 16-bit palette RAM, arranged as a 128x32-bit RAM.
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Frame, line, and pixel clock signals.
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AC bias signal for STN, data enable signal for TFT panels.
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Supports little and big-endian, and Windows CE data formats.
•
LCD panel clock may be generated from the peripheral clock, or from a clock input
pin.
UM10503
Chapter 27: LPC43xx LCD
Rev. 1.3 — 6 July 2012
User manual
Table 597. LCD clocking and power control
Base clock
Branch clock
Operating frequency
LCD register interface clock
BASE_M4_CLK
CLK_M4_LCD
up to 204 MHz
