UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
763 of 1269
NXP Semiconductors
UM10503
Chapter 27: LPC43xx LCD
27.4 General description
The LCD controller performs translation of pixel-coded data into the required formats and
timings to drive a variety of single or dual panel monochrome and color LCDs.
Packets of pixel coded data are fed using the AHB interface, to two independent,
programmable, 32-bit wide, DMA FIFOs that act as input data flow buffers.
The buffered pixel coded data is then unpacked using a pixel serializer.
Depending on the LCD type and mode, the unpacked data can represent:
•
An actual true display gray or color value.
•
An address to a 256x16 bit wide palette RAM gray or color value.
In the case of STN displays, either a value obtained from the addressed palette location,
or the true value is passed to the gray scaling generators. The hardware-coded gray scale
algorithm logic sequences the activity of the addressed pixels over a programmed number
of frames to provide the effective display appearance.
For TFT displays, either an addressed palette value or true color value is passed directly
to the output display drivers, bypassing the gray scaling algorithmic logic.
In addition to data formatting, the LCD controller provides a set of programmable display
control signals, including:
•
LCD panel power enable
•
Pixel clock
•
Horizontal and vertical synchronization pulses
•
Display bias
The LCD controller generates individual interrupts for:
•
Upper or lower panel DMA FIFO underflow
•
Base address update signification
•
Vertical compare
•
Bus error
There is also a single combined interrupt that is asserted when any of the individual
interrupts become active.
shows a simplified block diagram of the LCD controller.
