UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
375 of 1269
NXP Semiconductors
UM10503
Chapter 18: LPC43xx Serial GPIO (SGPIO)
18.8.1 Multi-channel I2S
18.8.1.1 I2S slice selection
A 5.1 channel I2S output interface in master mode requires 3 data outputs (SD[2:0]), 1
word select output (WS) and 1 clock output (SCK). In slave mode SCK becomes an input.
This means that output SCK should also support clock input. This is supported by pins
8-10 which are mapped in serial output mode to slices B, M, G or N, let's use slice B.
These slices should therefore not be used for SD or WS signals.
If an oversampled slave clock (MCK) is needed, use a slice that is capable to create
clocks for other slices (D, H, O or P), e.g. use slice D. In slave mode MCK is an input.
MCK is divided down to create the shift clock for Data, WS and SCK. In master mode
MCK is an output.
The output audio data rate is 6 x Fs. For Fs = 192 kHz this becomes 1.152 MWps and
thus relative low for a CPU frequency of 100+ MHz. Single slices can be used (without
concatenation), for example slices A, I and E. The WS is made by slice J. This results in
the following mapping:
Table 258. SGPIO Slice mapping for I2S 5.1
Slice: function
A,I,E : SD[2:0]
J : WS
B : SCK
D : MCK
Fig 40. 5.1 channel I2S output mapped to SGPIO slices
slice A
slice I
sckin
sd0
slice E
slice J
sck
mck
sd2
sd1
ws
slice B
counter D
mckin
pin 0
pin 1
pin 2
pin 3
pin 8
pin 12
counter A
counter I
counter E
counter J
slave to sck
slave to mck
counter B
sgpio _clk
slice D
MCK/4
