UM10503
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User manual
Rev. 1.3 — 6 July 2012
899 of 1269
NXP Semiconductors
UM10503
Chapter 31: LPC43xx Quadrature Encoder Interface (QEI)
Table 727: QEI Configuration register (CONF - address 0x400C 6008) bit description
Bit
Symbol
Description
Reset
value
0
DIRINV
Direction invert. When = 1, complements the DIR bit.
0
1
SIGMODE
Signal Mode. When = 0, PhA and PhB function as quadrature
encoder inputs. When = 1, PhA functions as the direction signal
and PhB functions as the clock signal.
0
2
CAPMODE Capture Mode. When = 0, only PhA edges are counted (2X).
When = 1, BOTH PhA and PhB edges are counted (4X),
increasing resolution but decreasing range.
0
3
INVINX
Invert Index. When set, inverts the sense of the index input.
0
4
CRESPI
Continuously reset position counter on index. When set = 1,
resets the position counter to all zeros when an index pulse
occurs at the next position increase (recalibration). Auto-clears
when the position counter is cleared.
0
15:5
-
Reserved
0
19:16
INXGATE
Index gating configuration:
when INXGATE(19)=1, pass the index when Pha=0 and Phb=0,
else block.
when INXGATE(18)=1, pass the index when Pha=0 and Phb=1,
else block.
when INXGATE(17)=1, pass the index when Pha=1 and Phb=1,
else block.
when INXGATE(16)=1, pass the index when Pha=1 and Phb=0,
else block.
1111
31:20
-
reserved
0
