NXP Semiconductors LCP43 Series, User Manual

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User manual Rev. 1.3 — 6 July 2012 625 of 1269
NXP Semiconductors
UM10503
Chapter 24: LPC43xx USB1 Host/Device controller
[1] There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware continuing to clear this bit. In most
systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice that the stall bit is not set after
writing a one to it, software should continually write this stall bit until it is set or until a new setup has been received by checking the
associated ENDPTSETUPSTAT bit.
24.6.23 Endpoint 1 to 3 control registers
Each endpoint that is not a control endpoint has its own register to set the endpoint type
and enable or disable the endpoint.
Remark: The reset value for all endpoint types is the control endpoint. If one endpoint
direction is enabled and the paired endpoint of opposite direction is disabled, then the
endpoint type of the unused direction must be changed from the control type to any other
type (e.g. bulk). Leaving an unconfigured endpoint control will cause undefined behavior
for the data PID tracking on the active endpoint.
16 TXS Tx endpoint stall R/W
0 Endpoint ok.
1 Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
After receiving a SETUP request, this bit will continue to be cleared
by hardware until the associated ENDSETUPSTAT bit is cleared.
[1]
17 - - Reserved
19:18 TXT 0x0 Endpoint type
Endpoint 0 is always a control endpoint.
0 RO
22:20 - - Reserved
23 TXE 1 Tx endpoint enable
Endpoint enabled. Control endpoint 0 is always enabled. This bit is
always 1.
1 RO
31:24 - - Reserved
Table 491. USB Endpoint 0 Control register (ENDPTCTRL0 - address 0x4000 71C0) bit description
…continued
Bit Symbol Value Description Reset
value Access
Table 492. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to
0x4000 71CC (ENDPTCTRL3)) bit description
Bit Symbol Value Description Reset
value Access
0 RXS Rx endpoint stall 0 R/W
0 Endpoint ok.
This bit will be cleared automatically upon receipt of a SETUP
request if this Endpoint is configured as a Control Endpoint and this
bit will continue to be cleared by hardware until the associated
ENDPTSETUPSTAT bit is cleared.
1 Endpoint stalled
Software can write a one to this bit to force the endpoint to return a
STALL handshake to the Host. It will continue returning STALL until
the bit is cleared by software, or it will automatically be cleared upon
receipt of a new SETUP request.
[1]