UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
709 of 1269
NXP Semiconductors
UM10503
Chapter 26: LPC43xx Ethernet
6
RI
Receive interrupt
This bit indicates the completion of frame reception. Specific frame status information
has been posted in the descriptor. Reception remains in the Running state.
0
R/W
7
RU
Receive buffer unavailable
This bit indicates that the Next Descriptor in the Receive List is owned by the host and
cannot be acquired by the DMA. Receive Process is suspended. To resume
processing Receive descriptors, the host should change the ownership of the
descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is
issued, Receive Process resumes when the next recognized incoming frame is
received. This bit is set only when the previous Receive Descriptor was owned by the
DMA.
0
R/W
8
RPS
Received process stopped
This bit is asserted when the Receive Process enters the Stopped state.
0
R/W
9
RWT
Receive watchdog timeout
This bit is asserted when a frame with a length greater than 2,048 bytes is received
(10,240 when Jumbo Frame mode is enabled).
0
R/W
10
ETI
Early transmit interrupt
This bit indicates that the frame to be transmitted was fully transferred to the MTL
Transmit FIFO.
0
R/W
12:11
-
Reserved
0 RO
13
FBI
Fatal bus error interrupt
This bit indicates that a bus error occurred, as detailed in bits [25:23]. When this bit is
set, the corresponding DMA engine disables all its bus accesses.
0
R/W
14
ERI
Early receive interrupt
This bit indicates that the DMA had filled the first data buffer of the packet. Receive
Interrupt bit 6 in this register automatically clears this bit.
0
R/W
Table 566. DMA Status register (DMA_STAT, address 0x4001 1014) bit description
…continued
Bit
Symbol
Description
Reset
value
Access
