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UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
718 of 1269
NXP Semiconductors
UM10503
Chapter 26: LPC43xx Ethernet
26.6.40 DMA Current host receive buffer address register
The Current Host Receive Buffer Address register points to the current Receive Buffer
address being read by the DMA.
26.7 Functional description
26.7.1 Power management block
This section describes the power management (PMT) mechanisms supported by the
MAC. PMT supports the reception of network (remote) wake-up frames and Magic Packet
frames. PMT does not perform the clock gate function, but generates interrupts for
wake-up frames and Magic Packets received by the MAC. The PMT block sits on the
receiver path of the MAC and is enabled with remote wake-up frame enable and Magic
Packet enable. These enables are in the PMT Control and Status register and are
programmed by the Application.
When the power-down mode is enabled in the PMT, then all received frames are dropped
by the core and they are not forwarded to the application. The core comes out of the
power down mode only when either a Magic Packet or a Remote Wake-up frame is
received and the corresponding detection is enabled.
26.7.1.1 Remote wake-up frame registers
The register WKUPFMFILTER_REG, address (0x028), loads the Wake-up Frame Filter
register. To load values in a Wake-up Frame Filter register, the entire register
(WKUPFMFILTER_REG) must be written. The WKUPFMFILTER_REG register is loaded
by sequentially loading the eight register values in address (0x028) for
WKUPFMFILTER_REG0, WKUPFMFILTER_REG1,... WKUPFMFILTER_REG7,
respectively. WKUPFMFILTER_REG is read in the same way.
Remark:
The internal counter to access the appropriate WKUPFMFILTER_REG is
incremented when lane 3 (or lane 0 in big-endian) is accessed by the CPU. This should be
kept in mind if you are accessing these registers in byte or half-word mode.
Table 573. DMA Current host transmit buffer address register
(DMA_CURHOST_TRANS_BUF, address 0x4001 1050) bit description
Bit
Symbol
Description
Reset
value
Access
31:0
HTB
Host Transmit Buffer Address Pointer
Cleared on Reset. Pointer updated by DMA during
operation.
0
RO
Table 574. DMA Current host receive buffer address register (DMA_CURHOST_REC_BUF,
address 0x4001 1054) bit description
Bit
Symbol
Description
Reset
value
Access
31:0
HRB
Host Receive Buffer Address Pointer
Cleared on Reset. Pointer updated by DMA during
operation.
0
RO