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NXP Semiconductors LCP43 Series, User Manual

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NXP Semiconductors LCP43 Series User Manual Download Page 854

UM10503

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© NXP B.V. 2012. All rights reserved.

User manual

Rev. 1.3 — 6 July 2012 

854 of 1269

NXP Semiconductors

UM10503

Chapter 29: LPC43xx Timer0/1/2/3

29.6.1 Timer interrupt registers

The Interrupt Register consists of four bits for the match interrupts and four bits for the 
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be 
high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset 
the interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match 
also clears any corresponding DMA request.

 

29.6.2 Timer control registers

The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.

 

29.6.3 Timer counter registers

The 32-bit Timer Counter register is incremented when the prescale counter reaches its 
terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will 
count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. 
This event does not cause an interrupt, but a match register can be used to detect an 
overflow if needed.

Table 684. Timer interrupt registers (IR - addresses 0x4008 4000 (TIMER0), 0x4008 5000 

(TIMER1), 0x400C 3000 (TIMER2), 0x400C 4000 (TIMER3)) bit description

Bit

Symbol

Description

Reset 
value

0

MR0INT

Interrupt flag for match channel 0.

0

1

MR1INT

Interrupt flag for match channel 1.

0

2

MR2INT

Interrupt flag for match channel 2.

0

3

MR3INT

Interrupt flag for match channel 3.

0

4

CR0INT

Interrupt flag for capture channel 0 event.

0

5

CR1INT

Interrupt flag for capture channel 1 event.

0

6

CR2INT

Interrupt flag for capture channel 2 event.

0

7

CR3INT

Interrupt flag for capture channel 3 event.

0

31:8

-

Reserved.

-

Table 685. Timer control register (TCR - addresses 0x4008 4004 (TIMER0), 0x4008 5004 

(TIMER1), 0x400C 3004 (TIMER2), 0x400C 4004 (TIMER3)) bit description

Bit

Symbol

Description

Reset value

0

CEN

When one, the Timer Counter and Prescale Counter are 
enabled for counting. When zero, the counters are 
disabled.

0

1

CRST

When one, the Timer Counter and the Prescale Counter 
are synchronously reset on the next positive edge of 
PCLK. The counters remain reset until TCR[1] is 
returned to zero.

0

31:2

-

Reserved, user software should not write ones to 
reserved bits. The value read from a reserved bit is not 
defined.

NA

Summary of Contents for LCP43 Series

Page 1: ...350FBD208 LPC4330FET256 LPC4330FET180 LPC4330FET100 LPC4330FBD144 LPC4320FET100 LPC4320FBD144 LPC4310FET100 LPC4310FBD144 LPC4357FET256 LPC4357FET180 LPC4357FBD208 LPC4353FET256 LPC4353FET180 LPC4353F...

Page 2: ...e for LPC43Sxx parts Bank Row Column addressing for SDRAM devices added in Table 373 Parts LPC4337 and LPC4333 added 1 2 20120608 LPC43xx user manual Modifications Syncflash removed from Chapter 21 Pa...

Page 3: ...LPC43xx I2S interface updated Remove condition RTC_ALARM LOW on reset for entering debug mode Ethernet chapter updated PPS and auxiliary timestamp features removed Chapter 36 LPC43xx Event monitor re...

Page 4: ...ortex M4 supports single cycle digital signal processing and SIMD instructions A hardware floating point processor is integrated in the core The ARM Cortex M0 coprocessor is an energy efficient and ea...

Page 5: ...ADC0 1 Serial interfaces Quad SPI Flash Interface SPIFI with 1 2 or 4 bit data at rates of up to 60 MB per second 10 100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput...

Page 6: ...t modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins Four general purpose timer counters with capture and match capabilities One motor control Pulse Wi...

Page 7: ...able as LBGA256 TFBGA180 and TFBGA100 packages and as LQFP208 and LQFP144 packages 1 3 Ordering information flashless parts LPC4350 30 20 10 Table 1 Ordering information Type number Package Name Descr...

Page 8: ...on LPC4357FET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 17 1 mm SOT740 2 LPC4357FET180 TFBGA180 Thin fine pitch ball grid array package 180 balls SOT570 3 LPC4357FBD208...

Page 9: ...yes yes yes yes yes 8 142 LPC4353FET256 512 kB 256 kB 256 kB 136 kB yes yes yes yes yes 8 164 LPC4353FET180 512 kB 256 kB 256 kB 136 kB yes yes yes yes yes 8 118 LPC4353FBD208 512 kB 256 kB 256 kB 13...

Page 10: ...OST DEVICE EMC HIGH SPEED PHY 32 kB AHB SRAM 16 16 kB AHB SRAM SPIFI AES HS GPIO SPI SGPIO SCT 64 kB ROM I2C0 I2S0 I2S1 C_CAN1 MOTOR CONTROL PWM 1 TIMER3 TIMER2 USART2 USART3 SSP1 RI TIMER QEI 1 GIMA...

Page 11: ...HOST DEVICE EMC HIGH SPEED PHY SPIFI HS GPIO SPI SGPIO SCT I2C0 I2S0 I2S1 C_CAN1 MOTOR CONTROL PWM TIMER3 TIMER2 USART2 USART3 SSP1 RI TIMER QEI GIMA BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE AHB MU...

Page 12: ...2 2 3 Introduction The LPC43xx is a dual core microcontroller implementing an ARM Cortex M4 and an ARM Cortex M0 core The ARM Cortex M4 is used as application processor The second core the ARM Cortex...

Page 13: ...signal TXEV This signal is captured by CREG It should be cleared by the interrupt handler of the receiving core 2 5 IPC Protocol description The IPC supports low level interfaces e g a register level...

Page 14: ...round to the start address When the read pointer is equal to the write pointer the queue can be either empty or completely full To avoid this ambiguity the queue shall never be filled completely The m...

Page 15: ...defines which task is referred to The LSBit indicates the command type A Write command is followed by a 32 bit operand When a new command is available the ARM Cortex M4 signals this to the ARM Cortex...

Page 16: ...lternative approach is that the ARM Cortex M4 writes register per register however this requires more communication overhead than loading all data in one go Once all data has been set up the ARM Corte...

Page 17: ...sses the registers 2 MSG_WR_STS 0x1234 rst 2 ARM Cortex M0 signals write data has been processed 3 MSR_SRV 0x1234 serve 00 ARM Cortex M0 requests service e g because data has been captured and is avai...

Page 18: ...used as normal SRAM on the AHB bus Remark When the ETB is used the 16 kB memory space at 0x2000 C000 must not be used by any other process 3 3 Memory configuration 3 3 1 On chip static RAM The LPC43x...

Page 19: ...lt in a bit write 3 3 3 On chip flash The available flash configuration for the LPC435x 3x 2x 1x is shown in Table 11 An integrated flash accelerator maximizes performance for use with the two fast AH...

Page 20: ...supported by all LPC43xx parts The processor supports the standard ARMv7 Protected Memory System Architecture model The MPU provides full support for protection regions overlapping protection regions...

Page 21: ...HB SRAM LPC4350 30 16 kB AHB SRAM LPC4350 30 20 10 0x2000 C000 16 kB AHB SRAM LPC4350 30 16 kB AHB SRAM LPC4350 30 20 10 SGPIO SPI AES 0x4010 1000 0x4010 2000 0x4200 0000 reserved local SRAM external...

Page 22: ...ripherals SGPIO SPI AES 0x4010 1000 0x4010 2000 0x4200 0000 reserved external memories and ARM private bus APB2 peripherals 0x400C 1000 0x400C 2000 0x400C 3000 0x400C 4000 0x400C 6000 0x400C 8000 0x40...

Page 23: ...iconductors UM10503 Chapter 3 LPC43xx Memory mapping 3 5 Memory map parts with on chip flash The memory map shown in Figure 6 and Figure 7 is global to both the Cortex M4 and the Cortex M0 processors...

Page 24: ...I 0x4010 1000 0x4010 2000 0x4200 0000 reserved local SRAM external static memory banks 0x2000 0000 0x2001 0000 128 MB dynamic external memory DYCS0 256 MB dynamic external memory DYCS1 256 MB dynamic...

Page 25: ...0x400C 3000 0x400C 4000 0x400C 6000 0x400C 8000 0x400C 7000 0x400C 5000 0x400C 0000 RI timer USART2 USART3 timer2 timer3 SSP1 QEI APB1 peripherals 0x400A 1000 0x400A 2000 0x400A 3000 0x400A 4000 0x400...

Page 26: ...ize can be up to 8 To optimize CPU performance low latency code should be stored in a memory that is not accessed by other bus masters especially masters that use a long burst size To optimize the CPU...

Page 27: ...yer matrix connections flashless parts ARM CORTEX M4 TEST DEBUG INTERFACE ARM CORTEX M0 TEST DEBUG INTERFACE DMA ETHERNET USB1 USB0 LCD SD MMC EXTERNAL MEMORY CONTROLLER APB RTC DOMAIN PERIPHERALS 16...

Page 28: ...ts with on chip flash ARM CORTEX M4 TEST DEBUG INTERFACE ARM CORTEX M0 TEST DEBUG INTERFACE DMA ETHERNET USB1 USB0 LCD SD MMC EXTERNAL MEMORY CONTROLLER APB RTC DOMAIN PERIPHERALS HIGH SPEED PHY Syste...

Page 29: ...4 OTP bits must be programmed by the user The virgin OTP state is all zeros A zero value can be overwritten by a one but a one in any of the OTP bits cannot be changed Programming the OTP requires a h...

Page 30: ...word 1 or AES key 1 word 1 2 2 User programmable initial state 0 0x028 32 bit General purpose OTP memory 1 word 2 or AES key 1 word 2 2 3 User programmable initial state 0 0x02C 32 bit General purpos...

Page 31: ...EMC 16 bit 0101 EMC 32 bit 0110 USB0 0111 USB1 1000 SPI via SSP 1001 UART3 29 Reserved Do not write to this bit 30 Reserved Do not write to this bit 31 JTAG_DISABLE If this bit set JTAG cannot be ena...

Page 32: ...e Table 2 Ptr to Device Table 0 otp_Init Ptr to Function 2 Ptr to Function 0 Ptr to Function 1 Ptr to Function n OTP Driver 0x1040 0104 Device 0 ROM Driver Table 0x1040 0100 0x1040 0104 0x1040 0108 Pt...

Page 33: ...general error codes 0x10 Reserved 0x14 Reserved 0x18 Reserved otp_ProgGP0 0x1C Programs the general purpose OTP memory GP0 Use only if the device is not AES capable Parameter unsigned data unsigned m...

Page 34: ...support LPC43Sxx only CMAC authentication on the boot image Secure booting from an encrypted image Supports development mode for booting from a plain text image Development mode is terminated by prog...

Page 35: ...l static memory such as NOR flash using CS0 and an 8 bit data bus EMC 16 bit 0 1 0 0 Boot from external static memory such as NOR flash using CS0 and a 16 bit data bus EMC 32 bit 0 1 0 1 Boot from ext...

Page 36: ...x should be compiled with entry point at 0x0000 0000 On AES capable LPC43xx with a programmed AES key the image and header are authenticated using the CMAC algorithm If authentication fails the device...

Page 37: ...d Header yes yes no no AES capable and CMAC active yes copy image to SRAM and calculate CMAC tag valid tag decrypt image in SRAM yes set Shadow Pointer 0x1000 0000 development mode yes no copy image t...

Page 38: ...ge with header or execute directly from the boot source if the boot source is memory mapped see Table 20 When no valid header is found then the CPU will try to execute code from the first location of...

Page 39: ...T of message M using a 128 bit block cipher AES and secret key K the CMAC tag generation process works as follows 1 Generate sub key K1 Calculate a temporary value K0 AESK 0 If msb K0 0 then K1 K0 1 e...

Page 40: ...ead from the image is the most significant byte of the first AES codeword CMAC is calculated over the header and encrypted image 5 3 5 Boot modes 5 3 5 1 UART boot mode Figure 13 details the boot flow...

Page 41: ...e configured as pull down but not actively driven After reading the header the address bits are extended to be in line with the image size as defined by HASH_SIZE e g if HASH_SIZE is 100 kB then pins...

Page 42: ...steps of the Quad SPI flash boot mode The execution of this mode occurs only if the boot mode is set accordingly see boot modes in Table 18 andTable 19 The boot code sets the SPIFI clock to 18 MHz at...

Page 43: ...Hz USB1 requires VBUS pin to be set correctly Initially the USB0 PHY is disabled to save some power After it is enabled enumeration can start The DFU class is used to download a boot image After recei...

Page 44: ...th on chip flash booting from an external source Fig 17 USB boot process Setup clock USB_CLK 60MHz Setup VBUS pin P2_5 Boot source USB1 USB0 Setup clock USB_CLK 480MHz Enable HS PHY DFU enumerate rece...

Page 45: ...part resides in the end user board A LOW level on pin P2_7 after reset indicates hardware request to enter ISP mode ISP commands include preparing the on chip flash for erase and write operation readi...

Page 46: ...code and data The LPC43Sxx offers hardware to protect the external image content and to accelerate processing for data decryption data integrity and proof of origin The hardware consists of One time p...

Page 47: ...olled through a set of simple API calls located in the LPC43Sxx ROM The API calls to the ROM are performed by executing functions which are pointed to by pointer within the ROM driver table 6 4 1 AES...

Page 48: ...the parts are not configured for encryption using aes_SetMode with this parameter returns an error 3 CBC decode AES_API_CMD_DECODE_CBC Return unsigned see general error codes aes_LoadKey1 0x08 Loads 1...

Page 49: ...he number of frames to decrypt is given by the value HASH_SIZE If more frames need to be decrypted then this needs to be done by the application It is possible to decrypt a frame of Cipher Text indepe...

Page 50: ...alent to multiplication by x and x2 in a finite field GF 2b Let signify a standard left shift operator 1 Calculate a temporary value k0 Ek 0 2 If msb k0 0 then k1 k0 1 else k1 k0 1 C where C is a cert...

Page 51: ...e stored in software The 128 bit AES init vector iv is used to randomize the encryption when the same data is encrypted multiple times The init vector does not have to be secret and is also used to de...

Page 52: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AES plain text Array of 16 bytes RAM address 0C0D0EOF 08090A0B 04050607 000102 03 AES plain text Array of 4 words 32 bits 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01...

Page 53: ...egal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 3 6 July 2012 53 of 1269 NXP Semiconductors UM10503 Chapter 6 LPC43xx Security API 1 Load the stored random number from the backup r...

Page 54: ...parts of the ARM Cortex M4 and M0 processors Tightly coupled interrupt controllers provides low interrupt latency NVICs control system exceptions and peripheral interrupts Software interrupt generati...

Page 55: ...om an external signal the NMI function must be connected to the related device pin P4_0 or PE_4 When connected a logic one on the pin will cause the NMI to be processed For details refer to the Cortex...

Page 56: ...T0 GPIO pin interrupt 0 33 49 0xC4 PIN_INT1 GPIO pin interrupt 1 34 50 0xC8 PIN_INT2 GPIO pin interrupt 2 35 51 0xCC PIN_INT3 GPIO pin interrupt 3 36 52 0xD0 PIN_INT4 GPIO pin interrupt 4 37 53 0xD4 P...

Page 57: ...D 8 24 0x60 M0_USB0 OTG interrupt 9 25 0x64 M0_USB1 10 26 0x68 M0_SCT SCT combined interrupt 11 27 0x6C M0_RITIMER_OR_ WWDT RI timer interrupt ORed with WWDT interrupt 12 28 0x70 M0_TIMER0 13 29 0x74...

Page 58: ...Interrupt Clear Pending Register 1 This register allows changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions 0 IABR0 RO 0x300 Int...

Page 59: ...ter is LOW When using events 4 and 5 activate the 32 kHz oscillator in the CREG0 register Table 43 8 3 General description The event router is used to process wake up events such as certain interrupts...

Page 60: ...agram WAKEUP3 2 WAKEUP1 0 Peripheral interrupts GIMA outputs 27 26 Reset NVIC CREG Core PMU Power regulator CCU wake up EVENT ROUTER Events 0 to 19 Table 29 Event router inputs Event Source Descriptio...

Page 61: ...match channel 2 of timer 0 See Table 149 Not active in Deep sleep Power down and Deep power down mode Use for wake up from Sleep mode 14 GIMA output 26 Output 6 of the combined timer ORed output of S...

Page 62: ...r event status register 0x0 Table 39 SET_STAT W 0xFEC Set event status register 0x0 Table 40 Table 32 Level configuration register HILO address 0x4004 4000 bit description Bit Symbol Value Description...

Page 63: ...the EDGE register is 1 1 Detect HIGH level of the RTC interrupt if bit 5 in the EDGE register is 0 Detect rising edge if bit 5 in the EDGE register is 1 6 BOD_L Level detect mode for BOD event 0 0 De...

Page 64: ...tect HIGH level of the SD MMC interrupt if bit 11 in the EDGE register is 0 Detect rising edge if bit 11 in the EDGE register is 1 12 CAN_L Level detect mode for C_CAN event 0 0 Detect LOW level of th...

Page 65: ...t if bit 15 in the EDGE register is 0 Detect falling edge if bit 15 in the EDGE register is 1 1 Detect HIGH level of the QEI interrupt if bit 15 in the EDGE register is 0 Detect rising edge if bit 15...

Page 66: ...ct of WAKEUP2 pin Detect falling edge if bit 2 in the HILO register is 0 Detect rising edge if bit 2 in the HILO register is 1 3 WAKEUP3_E Edge level detect mode for WAKEUP3 event The corresponding bi...

Page 67: ...10 USB1_E Edge level detect mode for USB1 event The corresponding bit in the EDGE register must be 0 0 0 Level detect 1 Edge detect of the USB1 interrupt Detect falling edge if bit 10 in the HILO regi...

Page 68: ...EDGE register must be 0 0 0 Level detect 1 Edge detect of GIMA output 27 Detect falling edge if bit 16 in the HILO register is 0 Detect rising edge if bit 16 in the HILO register is 1 18 17 Reserved 1...

Page 69: ...able bit 12 in the ENABLE register 13 TIM2_CLREN Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register 14 TIM6_CLREN Writing a 1 to this bit clears the event enable bit 14 in t...

Page 70: ...s bit sets the event enable bit 12 in the ENABLE register 13 TIM2_SETEN Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register 14 TIM6_SETEN Writing a 1 to this bit sets the event...

Page 71: ...er 14 output event has been raised 18 17 Reserved 19 RESET_ST A 1 in this bit shows that the reset event has been raised 31 20 Reserved Table 37 Event status register STATUS address 0x4004 4FE0 bit de...

Page 72: ...er 0 11 SDMMC_EN A 1 in this bit indicates that the SDMMC event has been enabled This event wakes up the chip and contributes to the event router interrupt when bit 0 1 in the STATUS register 0 12 CAN...

Page 73: ...ent bit 5 in the STATUS register 6 BOD_CLRST Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register 7 WWDT_CLRST Writing a 1 to this bit clears the STATUS event bit 7 in the STAT...

Page 74: ...iting a 1 to this bit sets the STATUS event bit 6 in the STATUS register 7 WWDT_SETST Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register 8 ETH_SETST Writing a 1 to this bit set...

Page 75: ...in the CREG registers are reserved The following registers or register bits are implemented only on parts with on chip flash USB0FLADJ register USB1FLADJ register FALSHCFGA register FLASHCFGB register...

Page 76: ...settings are controlled in the configuration register block ETB SRAM configuration BOD trip settings RTC Oscillator output DMA to peripheral muxing Ethernet mode Memory mapping Timer UART inputs USB...

Page 77: ...CREG2 RO 0x10C Chip configuration register 2 tbd tbd tbd tbd CREG3 RO 0x110 Chip configuration register 3 tbd tbd tbd tbd CREG4 RO 0x114 Chip configuration register 4 tbd tbd tbd tbd CREG5 R W 0x118 C...

Page 78: ...00 Name Access Address offset Description Reset value Reset value after EMC UART0 3 boot Reset value after USB0 1 boot Reference Table 43 CREG0 register CREG0 address 0x4004 3004 bit description Bit S...

Page 79: ...13 12 SAMPLECTRL SAMPLE pin input output control 0 R W 0x0 Reserved 0x1 Sample output from the event monitor recorder 0x2 Output from the event router 0x3 Reserved 15 14 WAKEUP0CTRL WAKEUP0 pin input...

Page 80: ...on Bit Symbol Value Description Reset value Access 4 0 Reserved 5 Reserved 0 6 M4TAPSEL JTAG debug select for M4 core 1 R W 0 Bypass JTAG debug 1 Enable JTAG debug 7 Reserved 0 8 Reserved 0 9 M0APPTAP...

Page 81: ...R W 0x0 Timer 2 match 0 0x1 USART2 transmit 0x2 SSP1 transmit 0x3 Reserved 13 12 DMAMUXPER6 Selects DMA to peripheral connection for DMA peripheral 6 0 R W 0x0 Timer 2 match 1 0x1 USART2 receive 0x2...

Page 82: ...eserved 23 22 DMAMUXPER11 Selects DMA to peripheral connection for DMA peripheral 11 0 R W 0x0 SSP1 receive 0x1 Reserved 0x2 USART0 transmit 0x3 Reserved 25 24 DMAMUXPER12 Select DMA to peripheral con...

Page 83: ...LASHCFG register control internal flash accelerator functions and should not be altered Table 47 Flash Accelerator Configuration for flash bank A register FLASHCFGA address 0x4004 3120 bit description...

Page 84: ...er of BASE_M4_CLK clocks used for a flash access Warning Improper setting of this value may result in incorrect operation of the device All other values are reserved tbd 0x0 1 BASE_M4_CLK clock Use fo...

Page 85: ...s are used without timer match outputs 11 5 Reserved 12 I2S0_TX_SCK_IN_SEL I2S0_TX_SCK input select 0 R W 0 I2S clock selected as defined by the I2S transmit mode register Table 910 1 Audio PLL PLL0AU...

Page 86: ...tion Bit Symbol Value Description Reset value Access 0 TXEVCLR Cortex M4 TXEV event 0 R W 0 Clear the TXEV event 1 No effect 31 1 Reserved Table 52 Part ID register CHIPID address 0x4004 3200 bit desc...

Page 87: ...register Remark This register is only implemented for parts with on chip flash See Section 9 1 The USB frame length adjust register is used to adjust any offset from the clock source that generates t...

Page 88: ...st register USB1FLADJ address 0x4004 3600 bit description Bit Symbol Description Reset value Access 5 0 FLTV Frame length timing value The frame length is given in the number of high speed bit times i...

Page 89: ...The wake up from any of the Power down modes will always result in the Active mode The LPC43xx supports five power modes in order from highest to lowest power consumption 1 Active mode 2 Sleep mode c...

Page 90: ...All SRAM memory except for the upper 8 kB of the local SRAM located at 0x1008 0000 all analog blocks and the BOD control circuit are powered down The Power down mode is entered by a WFI or WFE instruc...

Page 91: ...or LPC4350 30 starting at 0x1009 0000 for LPC4320 10 and parts with on chip flash starting at 0x1008 8000 10 3 Register description Table 57 Memory retention Mode 128 kB local SRAM starting at 0x1000...

Page 92: ...nge the default power state of the LPC43xx after the next transition to a reduced power state Table 59 Hardware sleep event enable register PD0_SLEEP0_HW_ENA address 0x4004 2000 bit description Bit Sy...

Page 93: ...mode Description PD0_SLEEP0_MODE register bit settings Deep sleep CPU peripherals analog USB PHY in retention mode all SRAM supplies in active mode BOD in power down mode 0x0030 00AA Power down CPU p...

Page 94: ...from low frequencies to mid range frequencies 90 MHz to 110 MHz and subsequently from mid level frequencies to high frequencies up to 204 MHz The recommended procedure to configure BASE_M4_CLK depend...

Page 95: ...odes The following procedure shows how to ramp up the BASE_M4_CLK clock from low frequencies to the high frequency range see Figure 24 This procedure applies after waking up from deep sleep or power d...

Page 96: ...ions with high accuracy the PLL1 for creating the core and peripheral clocks Oscillator control Clock generation and clock source multiplexing Integer dividers for clock output stages 11 4 General des...

Page 97: ...crystal oscillator are the XTAL pins The crystal oscillator creates one output to the clock source bus 3 PLLs PLL0USB PLL0AUDIO and PLL1 are controlled by the CGU Each PLL can select one input from th...

Page 98: ..._CLK 480 MHz Base clock for USB0 2 BASE_PERIPH_CLK 204 MHz Base clock for SGPIO peripheral 3 BASE_USB1_CLK 204 MHz Base clock for USB1 4 BASE_M4_CLK 204 MHz System base clock for ARM Cortex M4 core an...

Page 99: ...o no no no no IDIVD yes yes yes no no no no no IDIVE yes yes yes no no no no no Table 65 Clock sources for output stages Output stages d default clock source y yes clock source available n no clock so...

Page 100: ...d default clock source y yes clock source available n no clock source not available Clock sources BASE_SAFE_CLK BASE_USB0_CLK BASE_PERIPH_CLK BASE_USB1_CLK BASE_M4_CLK BASE_SPIFI_CLK BASE_SPI_CLK BAS...

Page 101: ...clock ENET_RX_CLK I Ethernet PHY receive clock CLKOUT O Clock output pin CGU_OUT0 O CGU spare output 0 CGU_OUT1 O CGU spare output 1 Table 67 Register overview CGU base address 0x4005 0000 Name Access...

Page 102: ...0x0100 0000 Table 82 IDIVC_CTRL R W 0x050 Integer divider C control register 0x0100 0000 0x0900 0808 0x0900 0808 Table 82 IDIVD_CTRL R W 0x054 Integer divider D control register 0x0100 0000 0x0100 00...

Page 103: ...E_VADC_CLK 0x0100 0000 0x0100 0000 0x0100 0000 Table 88 BASE_SDIO_CLK R W 0x090 Output stage 13 control register for base clock BASE_SDIO_CLK 0x0100 0000 0x0100 0000 0x0100 0000 Table 88 BASE_SSP0_CLK...

Page 104: ...tained by the following equation Note that the accuracy of this measurement can be affected by several factors 1 Quantization error is noticeable if the ratio between the two clocks is large e g 100 k...

Page 105: ...r value 0 R 23 MEAS Measure frequency 0 R W 0 RCNT and FCNT disabled 1 Frequency counters started 28 24 CLK_SEL Clock source selection for the clock to be measured All other values are reserved 0 R W...

Page 106: ...Oscillator low frequency mode crystal or external clock source 1 to 20 MHz Between 15 MHz and 20 MHz the state of the HF bit is don t care 1 Oscillator high frequency mode crystal or external clock so...

Page 107: ...x 0xFFFFFFFF 3 DIRECTO PLL0 direct output 0 R W 4 CLKEN PLL0 clock enable 0 R W 5 Reserved 6 FRM Free running mode 0 R W 7 Reserved 0 R W 8 Reserved Reads as zero Do not write one to this register 0 R...

Page 108: ...D SELR 0 11 6 3 4 PLL0USB NP divider register Remark The PLL NP divider register does not use the direct binary representations of N and P directly Instead it uses encoded versions NDEC and PDEC of N...

Page 109: ...Section 11 8 3 and Section 11 8 4 11 6 4 PLL0AUDIO registers The PLL0AUDIO provides a wide range of frequencies for audio applications and can be connected to multiple base clocks The PLL0AUDIO can b...

Page 110: ...direct input 0 R W 3 DIRECTO PLL0 direct output 0 R W 4 CLKEN PLL0 clock enable 0 R W 5 Reserved 6 FRM Free running mode 0 R W 7 Reserved 0 R W 8 Reserved Reads as zero Do not write one to this regist...

Page 111: ...coded into a 17 bit MDEC value The relationship between M and MDEC is expressed via the following pseudo code For specific examples see Section 11 8 3 and Section 11 8 4 M_max 0x00008000 x 0x00004000...

Page 112: ...i N i N_max i x x x 2 x 3 x 4 1 7 x 1 0x7F NENC 9 0 x The valid range for P is from 1 to 2 5 This value is encoded into a 7 bit PDEC value The relationship can be expressed through the following pseu...

Page 113: ...ted as input to the M divider 11 6 5 PLL1 registers The PLL1 is used for the core and all peripheral blocks 11 6 5 1 PLL1 status register 11 6 5 2 PLL1 control register Table 78 PLL0AUDIO fractional d...

Page 114: ...r normal operation 7 DIRECT PLL direct CCO output 0 R W 0 Disabled 1 Enabled 9 8 PSEL Post divider division ratio P The value applied is 2xP 01 R W 0x0 1 0x1 2 default 0x2 4 0x3 8 10 Reserved 11 AUTOB...

Page 115: ...served 0x0A Reserved 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 80 PLL1_CTRL register PLL1_CTRL address 0x4005 0044 bit description continued Bit Symbol Value Descript...

Page 116: ...IO 0x09 PLL1 31 29 Reserved Table 81 IDIVA control register IDIVA_CTRL address 0x4005 0048 bit description continued Bit Symbol Value Description Reset value Access Table 82 IDIVB C D control register...

Page 117: ...C IDIVA 31 29 Reserved Table 82 IDIVB C D control registers IDIVB_CTRL address 0x4005 004C IDIVC_CTRL address 0x4005 0050 IDIVC_CTRL address 0x4005 0054 bit description Bit Symbol Value Description Re...

Page 118: ...ection All other values are reserved 0x01 R W 0x00 32 kHz oscillator 0x01 IRC default 0x02 ENET_RX_CLK 0x03 ENET_TX_CLK 0x04 GP_CLKIN 0x06 Crystal oscillator 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 31 29...

Page 119: ...D Output stage power down 0 R W 0 Output stage enabled default 1 power down 10 1 Reserved 11 AUTOBLOCK Block clock automatically during frequency change 0 R W 0 Autoblocking disabled 1 Autoblocking en...

Page 120: ..._TX_CLK 0x04 GP_CLKIN 0x06 Crystal oscillator 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 86 BASE_PERIPH_CLK control register BASE_PERIPH_CLK a...

Page 121: ...N 0x06 Crystal oscillator 0x07 PLL0USB 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 87 BASE_USB1_CLK control register BASE_USB1_CLK address 0x40...

Page 122: ..._RX_CLK 0x03 ENET_TX_CLK 0x04 GP_CLKIN 0x06 Crystal oscillator 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 88 BASE_M4_CLK to BASE_UART3_CLK con...

Page 123: ...Reserved 0x06 Crystal oscillator 0x07 PLL0USB 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 89 BASE_OUT_CLK control register BASE_OUT_CLK address...

Page 124: ...NET_TX_CLK 0x04 GP_CLKIN 0x05 Reserved 0x06 Crystal oscillator 0x07 Reserved 0x08 PLL0AUDIO 0x09 PLL1 0x0C IDIVA 0x0D IDIVB 0x0E IDIVC 0x0F IDIVD 0x10 IDIVE 31 29 Reserved Table 90 BASE_APLL_CLK contr...

Page 125: ...de 11 7 3 Crystal oscillator The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU see Table 69 11 7 4 PLL0 PLL0USB and PLL0AUDIO The PLL blocks of the PLL0USB and PLL0AUDIO ar...

Page 126: ...dshake control Positive edge clocking Frequency limiter to avoid hang up of the PLL Lock detector Power down mode Free running mode Remark Both PLL0 blocks are functionally identical The PLL0 for audi...

Page 127: ...effectively prevents false lock indications and thus ensures a glitch free lock signal To avoid frequency hang up the PLL contains a frequency limiter This feature is built in to prevent the CCO from...

Page 128: ...e post divider 11 7 4 3 2 Mode 1a Normal operating mode without post divider and without pre divider In normal operating mode 1a the post divider and pre divider are bypassed The operating frequencies...

Page 129: ...5 Usage notes In order to set up the PLL0 follow these steps 1 Power down the PLL0 by setting bit 1 in the PLL0_CTRL register to 1 This step is only needed if the PLL0 is currently enabled 2 Configur...

Page 130: ...MHz input frequency The input from an external crystal is limited to 25 MHz 9 75 MHz to 320 MHz selectable output frequency with 50 duty cycle 156 MHz to 320 MHz Current Controlled Oscillator CCO fre...

Page 131: ...on to the input clock 11 7 6 3 Lock detector The lock detector measures the phase difference between the rising edges of the input and feedback clocks Only when this difference is smaller than the so...

Page 132: ...or 16 depending on the value of PSEL 1 0 automatically giving an output clock with a 50 duty cycle If a higher output frequency is needed the CCO clock can be sent directly to the output by setting DI...

Page 133: ...s disabled and the CCO clock is sent directly to the output leading to the following frequency equation 5 Power down mode In this mode the internal current reference will be turned off the oscillator...

Page 134: ...e BASE_APB1_CLK Using a crystal of 12 MHz as clock source a PLL1 multiplier of 10 and an integer divider of 4 provide the desired clock rate For this example program the CGU as follows 1 Enable the cr...

Page 135: ...Fclkin MHz PLL0USB_MDIV PLL0USB_NP_DIV Table 72 Table 73 1 0x073E 56C9 0x0030 2062 2 0x073E 2DAD 0x0030 2062 3 0x0B3E 34B1 0x0030 2062 4 0x0E3E 7777 0x0030 2062 5 0x0D32 6667 0x0030 2062 6 0x0B2A 2A66...

Page 136: ...2Fs 192 98 304 393 216 30 2 66 0x00002042 0x20c49b 96 49 152 491 52 11 514 5 0x00002005 0x147ae1 88 2 45 1584 451 584 2 1 5 0x00001005 0x1c3958 64 32 768 458 752 4 1 21 0x00001015 0x1cac08 48 24 576 5...

Page 137: ...ting for 12 MHz with fractional divider bypassed Fs KHz Fout MHz Fcco MHz Error Hz NDEC MDEC PDEC PLL0AUDIO_ MDIV PLL0AUDIO_ NP_DIV Table 76 Table 77 128 Fs 192 24 576 491 52 0 63 13523 14 0x000034d3...

Page 138: ...0x0003f018 24 12 288 368 64 0 63 2665 24 0x00000a69 0x0003f018 22 05 11 2896 338 688 0 45 18810 24 0x0000497a 0x0002d018 16 8 192 409 6 0 61 18724 6 0x00004924 0x0003d006 12 6 144 307 2 0 5 30580 6 0...

Page 139: ...clock divider Table 106 together with bit 16 in the CREG6 register Table 50 12 3 Features The CCUs switch the clocks to individual peripherals on or off Auto mode activates the AHB disable protocol b...

Page 140: ...I2S1 peripheral clock CLK_APB1_CAN1 Clock to the C_CAN1 register interface and C_CAN1 peripheral clock BASE_SPIFI_CLK CLK_SPIFI Clock for the SPIFI SCKI clock input BASE_M4_CLK CLK_M4_BUS M4 bus clock...

Page 141: ...mer3 register interface and timer3 peripheral clock CLK_M4_SSP1 Clock to the SSP1 register interface CLK_M4_QEI Clock to the QEI register interface and QEI peripheral clock BASE_PERIPH_ CLK CLK_PERIPH...

Page 142: ...PB3_ADC1 status register 0x0000 0001 Table 108 CLK_APB3_CAN0_CFG R W 0x128 CLK_APB3_CAN0 configuration register 0x0000 0001 Table 105 CLK_APB3_CAN0_STAT R 0x12C CLK_APB3_CAN0 status register 0x0000 00...

Page 143: ...W 0x448 CLK_M4_M4CORE configuration register 0x0000 0001 Table 105 CLK_M4_M4CORE_STAT R 0x44C CLK_M4_M4CORE status register 0x0000 0001 Table 108 0x450 to 0x45C Reserved 0x460 to 0x464 Reserved CLK_M...

Page 144: ...0001 Table 108 0x540 to 0x5FC Reserved CLK_M4_RITIMER_CFG R W 0x600 CLK_M4_RITIMER configuration register 0x0000 0001 Table 105 CLK_M4_RITIMER_STAT R 0x604 CLK_M4_RITIMER status register 0x0000 0001 T...

Page 145: ...U1 base address 0x4005 1000 Name Access Address offset Description Reset value Reference Table 101 Register overview CCU2 base address 0x4005 2000 Name Access Address offset Description Reset value Re...

Page 146: ...clock running Remark Reactivate the base clock before writing to the configuration register of the branch clock 0x508 to 0x5FC Reserved CLK_APB2_SSP1_CFG R W 0x600 CLK_APB2_SSP1 configuration register...

Page 147: ...Reserved 6 BASE_PERIPH_ CLK_IND Base clock indicator for BASE_PERIPH_CLK 0 All branch clocks switched off 1 At least one branch clock running 1 R 7 BASE_USB0_ CLK_IND Base clock indicator for BASE_USB...

Page 148: ...ve ensure that all transfers have completed before turning off the master clock in auto mode Otherwise data may be lost when the master clock is turned off and the master can t process a response from...

Page 149: ...ock is disabled 1 Clock is enabled 1 AUTO Auto AHB disable mechanism enable 0 R W 0 Auto is disabled 1 Auto is enabled 2 WAKEUP Wake up mechanism enable 0 R W 0 Wake up is disabled 1 Wake up is enable...

Page 150: ...able 107 CCU2 branch clock configuration register CLK_XXX_CFG addresses 0x4005 2100 0x4005 2200 0x4005 2800 bit description Bit Symbol Value Description Reset value Access 0 RUN Run enable 1 R W 0 Clo...

Page 151: ...CCU Table 109 CCU2 branch clock status register CLK_XXX_STAT addresses 0x4005 2104 0x4005 2204 0x4005 2804 bit description Bit Symbol Description Reset value Access 0 RUN Run enable status 0 clock is...

Page 152: ...l is asserted by a reset generator with one output the reset signal and one or more inputs which link the reset generators together and create a reset hierarchy Remark The ARM Cortex M4 SYSRESETREQ tr...

Page 153: ...egister block Event router backup registers RTC alarm timer No software reset Reserved 6 7 BUS_RST 8 PERIPH_RST Buses RGU CCU and CGU registers memory controllers bus bridges Do not use during normal...

Page 154: ...reset ADC register interface and analog block ADC1_RST 41 PERIPH_RST ADC1 reset ADC register interface and analog block DAC_RST 42 PERIPH_RST DAC reset DAC register interface and analog block Reserved...

Page 155: ...ut signal 13 3 1 Reset hierarchy The hierarchy is as follows see Table 112 1 External reset BOD reset signal WWDT time out and reset signal from the PMU 2 CORE_RST inputs are the external reset pin BO...

Page 156: ...1 see Table 115 RESET_STATUS0 R W 0x110 Reset status register 0 0x5555 0050 see Table 116 RESET_STATUS1 R W 0x114 Reset status register 1 0x5555 5555 see Table 117 RESET_STATUS2 R W 0x118 Reset status...

Page 157: ...x0 see Table 128 RESET_EXT_STAT20 R W 0x450 Reset external status register 20 for SDIO_RST 0x0 see Table 128 RESET_EXT_STAT21 R W 0x454 Reset external status register 21 for EMC_RST 0x0 see Table 128...

Page 158: ...AT45 R W 0x4B4 Reset external status register 45 for UART1_RST 0x0 see Table 127 RESET_EXT_STAT46 R W 0x4B8 Reset external status register 46 for UART2_RST 0x0 see Table 127 RESET_EXT_STAT47 R W 0x4BC...

Page 159: ...er overview RGU base address 0x4005 3000 continued Name Access Address offset Description Reset value Reference Table 114 Reset control register 0 RESET_CTRL0 address 0x4005 3100 bit description Bit S...

Page 160: ...one activates the reset This bit is automatically cleared to 0 after one clock cycle 0 W 29 FLASHB_RST Writing a one activates the reset This bit is automatically cleared to 0 after one clock cycle 0...

Page 161: ...cycle 0 W 17 I2C1_RST Writing a one activates the reset This bit is automatically cleared to 0 after one clock cycle 0 W 18 SSP0_RST Writing a one activates the reset This bit is automatically cleare...

Page 162: ...RESET_CTRL register 00 R W 3 2 PERIPH_RST Status of the PERIPH_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator this reset is self clearing 10...

Page 163: ...ymbol Description Reset value Access Table 117 Reset status register 1 RESET_STATUS1 address 0x4005 3114 bit description Bit Symbol Description Reset value Access 1 0 LCD_RST Status of the LCD_RST res...

Page 164: ...erved 01 17 16 Reserved 01 19 18 FLASHA_RST Status of the FLASHA_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator 10 Reserved 11 Reset output...

Page 165: ...y software write to RESET_CTRL register 01 R W 7 6 TIMER3_RST Status of the TIMER3_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator 10 Reserve...

Page 166: ...ister 01 R W 23 22 Reserved 01 R W 25 24 UART0_RST Status of the UART0_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator 10 Reserved 11 Reset o...

Page 167: ...ed by software write to RESET_CTRL register 01 R W 7 6 SSP1_RST Status of the SSP1_RST reset generator output 00 No reset activated 01 Reset output activated by input to the reset generator 10 Reserve...

Page 168: ...11 Reset output activated by software write to RESET_CTRL register 01 R W 21 20 SPI_RST Status of the SPI_RST reset generator output 00 No reset activated 01 Reset output activated by input to the res...

Page 169: ...he M4_RST 0 Reset asserted 1 No reset 0 R 14 Reserved 0 15 Reserved 0 16 LCD_RST Current status of the LCD_RST 0 Reset asserted 1 No reset 0 R 17 USB0_RST Current status of the USB0_RST 0 Reset assert...

Page 170: ...30 Reserved 31 Reserved Table 121 Reset active status register 1 RESET_ACTIVE_STATUS1 address 0x4005 3154 bit description Bit Symbol Description Reset value Access 0 TIMER0_RST Current status of the...

Page 171: ...asserted 1 No reset 0 R 11 12 UART0_RST Current status of the UART0_RST 0 Reset asserted 1 No reset 0 R 13 UART1_RST Current status of the UART1_RST 0 Reset asserted 1 No reset 0 R 14 UART2_RST Curre...

Page 172: ...All other reset generators have only one input which depending on the hierarchy can be either the CORE_RST the PERIPHERAL_RST or the MASTER_RST Note that the external status register does not show wh...

Page 173: ...egister Table 122 Reset external status register 0 RESET_EXT_STAT0 address 0x4005 3400 bit description Bit Symbol Description Reset value Access 0 EXT_RESET Reset activated by external reset from rese...

Page 174: ...0 Reserved Do not modify read as logic 0 0 2 PERIPHERAL_RESET Reset activated by PERIPHERAL_RST output Write 0 to clear 0 Reset not activated 1 Reset activated 0 R W 31 3 Reserved Do not modify read...

Page 175: ...e is dependent on the peripheral see Table 113 Table 127 Reset external status registers x RESET_EXT_STATx address 0x4005 34xx bit description Bit Symbol Description Reset value Access 1 0 Reserved Do...

Page 176: ...groups named P0 to P9 and PA to PF with up to 20 pins used per group Each digital pin may support up to eight different digital pin functions including General Purpose I O GPIO selectable through the...

Page 177: ...sponds to the signal WS in the I2S bus specification I O I2S1_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the I2S bus specification...

Page 178: ...SP0_MOSI Master Out Slave in for SSP0 R Function reserved R Function reserved P1_3 P5 M2 J1 61 44 3 N PU I O GPIO0 10 General purpose digital input output pin O CTOUT_8 SCT output 8 Match output 0 of...

Page 179: ...input output pin I CTIN_5 SCT input 5 Capture input 2 of timer 2 R Function reserved O EMC_WE LOW active Write Enable signal R Function reserved R Function reserved I O SGPIO14 General purpose digita...

Page 180: ...C_D2 External memory data line 2 R Function reserved R Function reserved R Function reserved I O SD_DAT0 SD MMC data bus line 0 P1_10 R8 N6 H6 75 53 3 N PU I O GPIO1 3 General purpose digital input ou...

Page 181: ...ture input 0 of timer 0 R Function reserved I O SGPIO9 General purpose digital input output pin I SD_CD SD MMC card detect input P1_14 R11 K7 J8 85 61 3 N PU I O GPIO1 7 General purpose digital input...

Page 182: ...I O SGPIO11 General purpose digital input output pin R Function reserved P1_18 N12 N10 J10 95 67 3 N PU I O GPIO0 13 General purpose digital input output pin I O U2_DIR RS 485 EIA 485 output enable di...

Page 183: ...t indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts I...

Page 184: ...O5 3 General purpose digital input output pin R Function reserved O T3_MAT0 Match output 0 of timer 3 O USB0_PPWR VBUS drive signal towards external charge pump or power management unit indicates that...

Page 185: ...al input output pin I O U0_DIR RS 485 EIA 485 output enable direction control for USART0 I O EMC_A10 External memory address line 10 O USB0_IND0 USB0 port indicator LED control output 0 I O GPIO5 6 Ge...

Page 186: ...t 3 of timer 0 I O U3_BAUD Baud pin for USART3 I O EMC_A0 External memory address line 0 R Function reserved R Function reserved R Function reserved R Function reserved P2_10 G16 F14 E8 146 104 3 N PU...

Page 187: ...mer 1 R Function reserved I O EMC_A4 External memory address line 4 R Function reserved R Function reserved R Function reserved I O U2_DIR RS 485 EIA 485 output enable direction control for USART2 P3_...

Page 188: ...he transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I O I2S0_RX_SDA I2S Receive data It is driven by the transmitter and read by the receiver Corresponds...

Page 189: ...15 General purpose digital input output pin R Function reserved R Function reserved I O SPIFI_SIO2 I O lane 2 for SPIFI I U1_RXD Receiver input for UART 1 I O I2S0_TX_SDA I2S transmit data It is driv...

Page 190: ...n in an input pin only The SPI in master mode cannot drive the CS input on the slave Any GPIO pin can be used for SPI chip select in master mode I O SSP0_MOSI Master Out Slave in for SSP0 I O SPIFI_CS...

Page 191: ...O GPIO2 2 General purpose digital input output pin O CTOUT_0 SCT output 0 Match output 0 of timer 0 O LCD_VD3 LCD data R Function reserved R Function reserved O LCD_VD12 LCD data I U3_RXD Receiver in...

Page 192: ...e SCU to select the DAC P4_5 D2 C2 15 10 3 N PU I O GPIO2 5 General purpose digital input output pin O CTOUT_5 SCT output 5 Match output 3 of timer 3 O LCD_FP Frame pulse STN Vertical synchronization...

Page 193: ...2 of timer 2 O LCD_VD9 LCD data R Function reserved I O GPIO5 12 General purpose digital input output pin O LCD_VD22 LCD data O CAN1_TD CAN1 transmitter output I O SGPIO13 General purpose digital inp...

Page 194: ...S 485 EIA 485 output enable signal for UART 1 I T1_CAP1 Capture input 1 of timer 1 R Function reserved R Function reserved P5_2 R4 M3 63 46 3 N PU I O GPIO2 11 General purpose digital input output pin...

Page 195: ...I U1_DCD Data Carrier Detect input for UART 1 O T1_MAT1 Match output 1 of timer 1 R Function reserved R Function reserved P5_6 T13 M11 89 63 3 N PU I O GPIO2 15 General purpose digital input output pi...

Page 196: ...output for USART0 in synchronous mode I O I2S0_RX_WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the I2S bus specification R Function rese...

Page 197: ...signal R Function reserved I T2_CAP2 Capture input 2 of timer 2 R Function reserved R Function reserved P6_4 R16 M14 F6 114 80 3 N PU I O GPIO3 3 General purpose digital input output pin I CTIN_6 SCT...

Page 198: ...General purpose digital input output pin O USB0_IND1 USB0 port indicator LED control output 1 I O GPIO5 15 General purpose digital input output pin O T2_MAT0 Match output 0 of timer 2 R Function reser...

Page 199: ...able 0 R Function reserved O T2_MAT3 Match output 3 of timer 2 R Function reserved R Function reserved P6_12 G15 F13 145 103 3 N PU I O GPIO2 8 General purpose digital input output pin O CTOUT_7 SCT o...

Page 200: ...ead by the receiver Corresponds to the signal SD in the I2S bus specification O LCD_VD18 LCD data O LCD_VD6 LCD data R Function reserved I U2_RXD Receiver input for USART2 I O SGPIO6 General purpose d...

Page 201: ...output pin O CTOUT_11 SCT output 1 Match output 3 of timer 2 R Function reserved O LCD_LP Line synchronization pulse STN Horizontal synchronization pulse TFT R Function reserved O TRACEDATA 2 Trace d...

Page 202: ...LED control output 1 R Function reserved I MCI1 Motor control PWM channel 1 input I O SGPIO9 General purpose digital input output pin R Function reserved R Function reserved O T0_MAT1 Match output 1 o...

Page 203: ...Function reserved I T0_CAP1 Capture input 1 of timer 0 P8_6 K3 J3 43 3 N PU I O GPIO4 6 General purpose digital input output pin I USB1_ULPI_NXT ULPI link NXT signal Data flow control signal from the...

Page 204: ...al purpose digital input output pin O MCOA2 Motor control PWM channel 2 output A R Function reserved R Function reserved I O I2S0_TX_WS Transmit Word Select It is driven by the master and received by...

Page 205: ...General purpose digital input output pin O ENET_TXD2 Ethernet transmit data 2 MII interface I O SGPIO4 General purpose digital input output pin I U3_RXD Receiver input for USART3 P9_5 M9 L7 98 69 3 N...

Page 206: ...L10 126 3 N PU R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved O I2S1_RX_MCLK I2S1 receive master clock O CGU_OUT1 CGU spare clock output 1 R Functi...

Page 207: ...9 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PB_0 B15 D14 164 3 N PU R Function reserved O CTOUT_10 SCT output 10 Match output 3 of timer 3 O...

Page 208: ...eral purpose digital input output pin O CTOUT_8 SCT output 8 Match output 0 of timer 2 R Function reserved R Function reserved PB_4 B11 B10 180 3 N PU R Function reserved I O USB1_ULPI_D5 ULPI link bi...

Page 209: ...1_ULPI_CLK ULPI link CLK signal 60 MHz clock generated by the PHY R Function reserved I O ENET_RX_CLK Ethernet Receive Clock MII interface O LCD_DCLK LCD panel clock R Function reserved R Function res...

Page 210: ...l input output pin R Function reserved R Function reserved O SD_VOLT1 SD MMC bus voltage select output 1 AI ADC1_0 ADC1 input channel 0 Configure the pin as GPIO input and use the ADC function select...

Page 211: ...ut output pin R Function reserved O T3_MAT0 Match output 0 of timer 3 I O SD_DAT3 SD MMC data bus line 3 PC_8 N4 3 N PU R Function reserved I O USB1_ULPI_D0 ULPI link bidirectional data line 0 R Funct...

Page 212: ...U R Function reserved R Function reserved O U1_DTR Data Terminal Ready output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 R Function reserved I O GPIO6 11...

Page 213: ...O GPIO6 14 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO4 General purpose digital input output pin PD_1 P1 3 N PU R Function reserved R Function reserved...

Page 214: ...igital input output pin R Function reserved R Function reserved I O SGPIO8 General purpose digital input output pin PD_5 P6 3 N PU R Function reserved O CTOUT_9 SCT output 9 Match output 3 of timer 3...

Page 215: ...ital input output pin R Function reserved R Function reserved I O SGPIO12 General purpose digital input output pin PD_9 T11 84 3 N PU R Function reserved O CTOUT_13 SCT output 13 Match output 3 of tim...

Page 216: ...pose digital input output pin R Function reserved O CTOUT_10 SCT output 10 Match output 3 of timer 3 R Function reserved PD_13 T14 97 3 N PU R Function reserved I CTIN_0 SCT input 0 Capture input 0 of...

Page 217: ...30 General purpose digital input output pin O SD_VOLT2 SD MMC bus voltage select output 2 O CTOUT_12 SCT output 12 Match output 3 of timer 3 R Function reserved PE_0 P14 N12 106 3 N PU R Function res...

Page 218: ...utput pin R Function reserved R Function reserved R Function reserved PE_4 K13 J11 120 3 N PU R Function reserved I NMI External interrupt input to NMI R Function reserved I O EMC_A22 External memory...

Page 219: ...6 I O GPIO7 7 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_8 F14 150 3 N PU R Function reserved O CTOUT_4 SCT output 4 Match output 3 of time...

Page 220: ...memory data line 30 I O GPIO7 11 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_12 D15 3 N PU R Function reserved O CTOUT_11 SCT output 11 Matc...

Page 221: ...SDRAM clock enable 3 I O GPIO7 15 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PF_0 D12 159 3 O PU I O SSP0_SCK Serial clock for SSP0 I GP_CLKI...

Page 222: ...172 120 3 O PU I O SSP1_SCK Serial clock for SSP1 I GP_CLKIN General purpose clock input to the CGU O TRACECLK Trace clock R Function reserved R Function reserved R Function reserved O I2S0_TX_MCLK I2...

Page 223: ...n for SSP1 O TRACEDATA 2 Trace data bit 2 I O GPIO7 21 General purpose digital input output pin R Function reserved I O SGPIO6 General purpose digital input output pin I O I2S1_TX_WS Transmit Word Sel...

Page 224: ...XD Transmitter output for USART0 R Function reserved R Function reserved I O GPIO7 24 General purpose digital input output pin R Function reserved I SD_WP SD MMC card write protect input R Function re...

Page 225: ...O I2S1_TX_MCLK I2S1 transmit master clock CLK2 D14 P10 K6 141 99 5 O PU O EMC_CLK3 SDRAM clock 3 O CLKOUT Clock output pin R Function reserved R Function reserved I O SD_CLK SD MMC card clock O EMC_CL...

Page 226: ...evice USB0_ID HIGH For OTG this pin has an internal pull up resistor USB0_RREF H1 G1 F3 32 24 9 12 0 k accuracy 1 on board resistor to ground for current reference USB1 pins USB1_DP F12 D11 E9 129 89...

Page 227: ...channel 5 Shared between 10 bit ADC0 1 ADC0_6 ADC1_6 A5 A4 204 142 9 I IA I ADC input channel 6 Shared between 10 bit ADC0 1 ADC0_7 ADC1_7 C5 B5 197 136 9 I IA I ADC input channel 7 Shared between 10...

Page 228: ...ly voltages VPP E8 13 OTP programming voltage VDDIO D7 E12 F7 F8 G10 H10 J6 J7 K7 L9 L10 N7 N13 H5 H10 K8 F10 K5 6 52 57 102 110 155 160 202 5 36 41 71 77 107 111 141 13 I O power supply Tie the VDDRE...

Page 229: ...When configured as a ADC input or DAC output the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull up resistor...

Page 230: ...PIO0 1 General purpose digital input output pin I O SSP1_MOSI Master Out Slave in for SSP1 I ENET_COL Ethernet Collision detect MII interface I O SGPIO1 General purpose digital input output pin R Func...

Page 231: ...for SSP1 R Function reserved O SD_RST SD MMC reset signal for MMC4 4 card P1_4 T3 P2 64 3 N PU I O GPIO0 11 General purpose digital input output pin O CTOUT_9 SCT output 9 Match output 3 of timer 3 I...

Page 232: ...pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB_PPWR u...

Page 233: ...3 I O EMC_D4 External memory data line 4 R Function reserved R Function reserved R Function reserved I O SD_DAT2 SD MMC data bus line 2 P1_12 R9 P7 78 3 N PU I O GPIO1 5 General purpose digital input...

Page 234: ...0_MAT1 Match output 1 of timer 0 R Function reserved I O EMC_D8 External memory data line 8 R Function reserved P1_16 M7 L5 90 3 N PU I O GPIO0 3 General purpose digital input output pin I U2_RXD Rece...

Page 235: ..._REF_CLK Ethernet Transmit Clock MII interface or Ethernet Reference Clock RMII interface I O SSP1_SCK Serial clock for SSP1 R Function reserved R Function reserved O CLKOUT Clock output pin R Functio...

Page 236: ...P2_1 N15 M13 116 3 N PU I O SGPIO5 General purpose digital input output pin I U0_RXD Receiver input for USART0 See Table 18 for ISP mode I O EMC_A12 External memory address line 12 I USB0_PWR_FAULT Po...

Page 237: ...arts P2_4 K11 L9 128 4 N PU I O SGPIO13 General purpose digital input output pin I O I2C1_SCL I2C1 clock input output this pin does not use a specialized I2C pad I U3_RXD Receiver input for USART3 See...

Page 238: ...CT output 1 Match output 3 of timer 3 I O U3_UCLK Serial clock input output for USART3 in synchronous mode I O EMC_A9 External memory address line 9 R Function reserved R Function reserved O T3_MAT3 M...

Page 239: ...2 I O EMC_A2 External memory address line 2 R Function reserved R Function reserved R Function reserved R Function reserved P2_12 E15 D13 153 3 N PU I O GPIO1 12 General purpose digital input output p...

Page 240: ...responds to the signal WS in the I2S bus specification I O I2S0_RX_WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the I2S bus specification...

Page 241: ...1_TXD Transmitter output for UART 1 I O I2S0_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the I2S bus specification I O I2S1_RX_SDA I...

Page 242: ...ut output pin I O SSP0_MOSI Master Out Slave in for SSP0 R Function reserved R Function reserved P3_8 C10 C9 179 3 N PU R Function reserved I SPI_SSEL Slave Select for SPI Note that this pin in an inp...

Page 243: ...elect the ADC P4_2 D3 A2 12 3 N PU I O GPIO2 2 General purpose digital input output pin O CTOUT_0 SCT output 0 Match output 0 of timer 0 O LCD_VD3 LCD data R Function reserved R Function reserved O LC...

Page 244: ...ion pulse TFT R Function reserved R Function reserved R Function reserved R Function reserved I O SGPIO11 General purpose digital input output pin P4_6 C1 B1 17 3 N PU I O GPIO2 6 General purpose digi...

Page 245: ...O GPIO5 13 General purpose digital input output pin O LCD_VD15 LCD data I CAN1_RD CAN1 receiver input I O SGPIO14 General purpose digital input output pin P4_10 M3 L3 51 3 N PU R Function reserved I...

Page 246: ...memory data line 14 R Function reserved O U1_RTS Request to Send output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 I T1_CAP2 Capture input 2 of timer 1 R...

Page 247: ...ta line 10 R Function reserved O U1_TXD Transmitter output for UART 1 O T1_MAT2 Match output 2 of timer 1 R Function reserved R Function reserved P5_7 R12 N11 91 3 N PU I O GPIO2 7 General purpose dig...

Page 248: ...485 EIA 485 output enable direction control for USART0 I O I2S0_RX_SDA I2S Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specificati...

Page 249: ...ction reserved R Function reserved R Function reserved P6_6 L14 K12 119 3 N PU I O GPIO0 5 General purpose digital input output pin O EMC_BLS1 LOW active Byte Lane select signal 1 I O SGPIO5 General p...

Page 250: ...in R Function reserved R Function reserved O EMC_DYCS0 SDRAM chip select 0 R Function reserved O T2_MAT2 Match output 2 of timer 2 R Function reserved R Function reserved P6_10 H15 G13 142 3 N PU I O...

Page 251: ...l input output pin P7_1 C14 C13 162 3 N PU I O GPIO3 9 General purpose digital input output pin O CTOUT_15 SCT output 15 Match output 3 of timer 3 I O I2S0_TX_WS Transmit Word Select It is driven by t...

Page 252: ...C0 input channel 4 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P7_5 A7 C7 191 6 N PU I O GPIO3 13 General purpose digital input output pin O C...

Page 253: ...nitors over current on the USB bus external circuitry required to detect over current condition R Function reserved I MCI2 Motor control PWM channel 2 input I O SGPIO8 General purpose digital input ou...

Page 254: ...O LCD_VD7 LCD data O LCD_VD16 LCD data R Function reserved R Function reserved I T0_CAP0 Capture input 0 of timer 0 P8_5 J1 H1 40 3 N PU I O GPIO4 5 General purpose digital input output pin I O USB1_...

Page 255: ...e clock output 0 O I2S1_TX_MCLK I2S1 transmit master clock P9_0 T1 P1 59 3 N PU I O GPIO4 12 General purpose digital input output pin O MCABORT Motor control PWM LOW active fast abort R Function reser...

Page 256: ...e I O SGPIO9 General purpose digital input output pin O U3_TXD Transmitter output for USART3 P9_4 N10 M8 92 3 N PU R Function reserved O MCOB0 Motor control PWM channel 0 output B O USB1_IND0 USB1 Por...

Page 257: ...Receiver input for USART0 PA_0 L12 L10 126 3 N PU R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved O I2S1_RX_MCLK I2S1 receive master clock O CGU_OU...

Page 258: ...al memory address line 23 I O GPIO5 19 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PB_0 B15 D14 164 3 N PU R Function reserved O CTOUT_10 SCT o...

Page 259: ...R Function reserved I O GPIO5 23 General purpose digital input output pin O CTOUT_8 SCT output 8 Match output 0 of timer 2 R Function reserved R Function reserved PB_4 B11 B10 180 3 N PU R Function r...

Page 260: ...k MII interface O LCD_DCLK LCD panel clock R Function reserved R Function reserved I O SD_CLK SD MMC card clock AI ADC1_1 ADC1 input channel 1 Configure the pin as GPIO input and use the ADC function...

Page 261: ...I O USB1_ULPI_D4 ULPI link bidirectional data line 4 R Function reserved ENET_TX_EN Ethernet transmit enable RMII MII interface I O GPIO6 3 General purpose digital input output pin R Function reserved...

Page 262: ...IO6 7 General purpose digital input output pin R Function reserved O T3_MAT1 Match output 1 of timer 3 I SD_CD SD MMC card detect input PC_9 K2 3 N PU R Function reserved I USB1_ULPI_NXT ULPI link NXT...

Page 263: ...input output pin I O I2S0_TX_SDA I2S transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I O SD_DAT5 SD MMC data bus line 5...

Page 264: ...PIO6 15 General purpose digital input output pin O SD_POW SD MMC power monitor output R Function reserved I O SGPIO5 General purpose digital input output pin PD_2 R1 3 N PU R Function reserved O CTOUT...

Page 265: ...rved I O GPIO6 19 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO9 General purpose digital input output pin PD_6 R6 68 3 N PU R Function reserved O CTOUT_10...

Page 266: ...rved I O GPIO6 23 General purpose digital input output pin R Function reserved R Function reserved I O SGPIO13 General purpose digital input output pin PD_10 P11 86 3 N PU R Function reserved I CTIN_1...

Page 267: ...2 R Function reserved I O GPIO6 27 General purpose digital input output pin R Function reserved O CTOUT_13 SCT output 13 Match output 3 of timer 3 R Function reserved PD_14 R13 L11 99 3 N PU R Functi...

Page 268: ...erved I O EMC_A18 External memory address line 18 I O GPIO7 0 General purpose digital input output pin O CAN1_TD CAN1 transmitter output R Function reserved R Function reserved PE_1 N14 M12 112 3 N PU...

Page 269: ...purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_5 N16 122 3 N PU R Function reserved O CTOUT_3 SCT output 3 Match output 3 of timer 0 O U1_RTS Request...

Page 270: ...GPIO7 8 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_9 E16 152 3 N PU R Function reserved I CTIN_4 SCT input 4 Capture input 2 of timer 1 I...

Page 271: ...O EMC_D31 External memory data line 31 I O GPIO7 12 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE_13 G14 3 N PU R Function reserved O CTOUT_14...

Page 272: ...lock input to the CGU R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved O I2S1_TX_MCLK I2S1 transmit master clock PF_1 E11 3 N PU R Function reserved...

Page 273: ...Trace clock R Function reserved R Function reserved R Function reserved O I2S0_TX_MCLK I2S transmit master clock I O I2S0_RX_SCK I2S receive clock It is driven by the master and received by the slave...

Page 274: ...ART3 I O SSP1_MOSI Master Out Slave in for SSP1 O TRACEDATA 2 Trace data bit 2 I O GPIO7 21 General purpose digital input output pin R Function reserved I O SGPIO6 General purpose digital input output...

Page 275: ...10 A3 205 6 N PU R Function reserved O U0_TXD Transmitter output for USART0 R Function reserved R Function reserved I O GPIO7 24 General purpose digital input output pin R Function reserved I SD_WP SD...

Page 276: ...ed O I2S1_TX_MCLK I2S1 transmit master clock CLK2 D14 P10 141 5 O PU O EMC_CLK3 SDRAM clock 3 O CLKOUT Clock output pin R Function reserved R Function reserved I O SD_CLK SD MMC card clock O EMC_CLK23...

Page 277: ...stor of 33 2 USB1_DM G12 E11 130 10 I O USB1 bidirectional D line Add an external series resistor of 33 2 I2C bus pins I2C0_SCL L15 K13 132 11 I F I O I2C clock input output Open drain output for I2C...

Page 278: ...the RTC 32 kHz ultra low power oscillator circuit RTCX2 B8 A7 183 9 O Output from the RTC 32 kHz ultra low power oscillator circuit SAMPLE B9 B8 12 O O Event monitor sample output Crystal oscillator...

Page 279: ...gital I O functions with TTL levels and hysteresis high drive strength 4 5 V tolerant pad with 15 ns glitch filter 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V provides high...

Page 280: ...if VDDIO not present do not exceed 3 6 V It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only 10 Open drain 5 V tolerant digital I O pad compatible...

Page 281: ...the multiplexed pins or the I2C0 pins as inputs set the corresponding pin configuration registers as follows Enable the input buffer by setting bit EZI to 1 For high frequency signals disable the inpu...

Page 282: ...ll up or pull down resistors with a typical value of 50 k for each pin or the selection of the repeater mode The possible on chip resistor configurations are pull up enabled pull down enabled or no pu...

Page 283: ...and speed or higher noise and speed see Figure 32 The typical frequencies supported are 50 MHz 80 MHz for normal drive pins and 75 MHz 204 MHz for high speed pins 15 3 6 High speed pins The clock pins...

Page 284: ...unt the changes performed by the boot loader Table 132 Register overview System Control Unit SCU base address 0x4008 6000 Name Access Address offset Description Reset value Reset value after EMC boot...

Page 285: ...egister for pin P2_2 0x00 0xD2 Table 133 SFSP2_3 R W 0x10C Pin configuration register for pin P2_3 0x00 0x00 0xD2 UART 3 Table 134 SFSP2_4 R W 0x110 Pin configuration register for pin P2_4 0x00 0x00 0...

Page 286: ...4_6 R W 0x218 Pin configuration register for pin P4_6 0x00 0x00 0x00 Table 133 SFSP4_7 R W 0x21C Pin configuration register for pin P4_7 0x00 0x00 0x00 Table 133 SFSP4_8 R W 0x220 Pin configuration re...

Page 287: ...0x00 Table 133 SFSP7_2 R W 0x388 Pin configuration register for pin P7_2 0x00 0x00 0x00 Table 133 SFSP7_3 R W 0x38C Pin configuration register for pin P7_3 0x00 0x00 0x00 Table 133 SFSP7_4 R W 0x390...

Page 288: ...00 Table 133 0x514 0x57C Reserved Pins PB_n SFSPB_0 R W 0x580 Pin configuration register for pin PB_0 0x00 0x00 0x00 Table 133 SFSPB_1 R W 0x584 Pin configuration register for pin PB_1 0x00 0x00 0x00...

Page 289: ...or pin PD_6 0x00 0x00 0x00 Table 133 SFSPD_7 R W 0x69C Pin configuration register for pin PD_7 0x00 0x00 0x00 Table 133 SFSPD_8 R W 0x6A0 Pin configuration register for pin PD_8 0x00 0x00 0x00 Table 1...

Page 290: ...er for pin PF_2 0x00 0x00 0x00 Table 133 SFSPF_3 R W 0x78C Pin configuration register for pin PF_3 0x00 0x00 0x00 Table 133 SFSPF_4 R W 0x790 Pin configuration register for pin PF_4 0x00 0x00 0x00 Tab...

Page 291: ...SB1 USB1_DP USB1_DM pins and I2C bus open drain pins SFSUSB R W 0xC80 Pin configuration register for pins USB1_DM and USB1_DP 0x02 0x00 0x00 Table 136 SFSI2C0 R W 0xC84 Pin configuration register for...

Page 292: ...n Reset value Access 2 0 MODE Select pin function 0 R W 0x0 Function 0 default 0x1 Function 1 0x2 Function 2 0x3 Function 3 0x4 Function 4 0x5 Function 5 0x6 Function 6 0x7 Function 7 3 EPD Enable pul...

Page 293: ...ll down 1 Enable pull down Enable both pull down resistor and pull up resistor for repeater mode 4 EPUN Disable pull up resistor at pad By default the pull up resistor is enabled at reset 0 R W 0 Enab...

Page 294: ...x4008 6C0C SFSCLK3 bit description Bit Symbol Value Description Reset value Access 2 0 MODE Select pin function 0 R W 0x0 Function 0 default 0x1 Function 1 0x2 Function 2 0x3 Function 3 0x4 Function 4...

Page 295: ...connected 3 Reserved 4 USB_EPWR Power mode 0 R W 0 Power saving mode Suspend mode 1 Normal mode 5 USB_VBUS Enable the vbus_valid signal This signal is monitored by the USB1 block Use this bit for sof...

Page 296: ...ed 1 Enabled 6 4 Reserved 7 SCL_ZIF Enable or disable input glitch filter for the SCL pin The filter time constant is determined by bit EFP 0 R W 0 Enable input filter 1 Disable input filter 8 SDA_EFP...

Page 297: ...1 in the ENAIO0 register Table 138 Pins controlled by the ENAIO0 register Pin ADC function ENAIO0 register bit P4_3 ADC0_0 0 P4_1 ADC0_1 1 PF_8 ADC0_2 2 P7_5 ADC0_3 3 P7_4 ADC0_4 4 PF_10 ADC0_5 5 PB_...

Page 298: ...PIO function in input mode 2 Disable the receiver by setting the EZI bit to zero see Table 133 or Table 134 This is the default setting 3 Disable the pull up resistor by setting the EPUN bit to one an...

Page 299: ...l function selected on pin PC_0 1 Analog function ADC1_1 selected on pin PC_0 2 ADC1_2 Select ADC1_2 0 R W 0 Digital function selected on pin PF_9 1 Analog function ADC1_2 selected on pin PF_9 3 ADC1_...

Page 300: ...ect the ADC1_7 input to the digital pad Set register ENAIO1at 0x4008 6C8C to 0x80 3 Connect the band gap to the digital pad Set register ENAIO2 at 0x4008 6C90 to 0x10 4 Do not connect pin PF_7 on the...

Page 301: ...x4008 6D00 bit description Bit Symbol Description Reset value Access 15 0 CLK_DELAY EMC_CLKn SDRAM clock output delay 0x0 no delay 0x1111 0 5 ns delay 0x2222 1 0 ns delay 0x3333 1 5 ns delay 0x4444 2...

Page 302: ...Port 2 0x3 GPIO Port 3 0x4 GPIO Port 4 0x5 GPIO Port 5 0x6 GPIO Port 6 0x7 GPIO Port 7 20 16 INTPIN2 Pint interrupt 2 Select the pin number within the GPIO port selected by the PORTSEL2 bit in this r...

Page 303: ...Port 1 0x2 GPIO Port 2 0x3 GPIO Port 3 0x4 GPIO Port 4 0x5 GPIO Port 5 0x6 GPIO Port 6 0x7 GPIO Port 7 12 8 INTPIN5 Pint interrupt 5 Select the pin number within the GPIO port selected by the PORTSEL...

Page 304: ...Control Unit SCU IO configuration 31 29 PORTSEL7 Pin interrupt 7 Select the port for the pin number to be selected in the INTPIN7 bits of this register 0 0x0 GPIO Port 0 0x1 GPIO Port 1 0x2 GPIO Port...

Page 305: ...ADCs the SCT or the timers Each output of the GIMA is connected to a peripheral function for example a timer capture input or an ADC conversion trigger input and configured through one register which...

Page 306: ...the events that can be selected for this GIMA output For signals that originate from an external pin select a pin from the pinout more than one pins may be possible and program the corresponding pin...

Page 307: ...el 1 pin CTIN_1 USART2 TX active I2S1_RX_MWS pin T2_CAP1 Table 159 10 T2 capture channel 2 pin CTIN_5 USART2 RX active I2S1_TX_MWS pin T2_CAP2 Table 160 11 T2 capture channel 3 SCT output 7 or T1 matc...

Page 308: ...rsion inverts the path between source and destination 3 Asynchronous capture 4 Synchronization to peripheral clock 5 Pulse generation 26 Event router input 14 SCT output 6 or T1 match channel 2 SGPIO1...

Page 309: ...multiplexer GIMA output 7 0 Table 157 CAP2_0_IN R W 0x020 Timer 2 CAP2_0 capture input multiplexer GIMA output 8 0 Table 158 CAP2_1_IN R W 0x024 Timer 2 CAP2_1 capture input multiplexer GIMA output 9...

Page 310: ...UTER_16_IN R W 0x06C Event router input 16 multiplexer GIMA output 27 0 Table 177 ADCSTART0_IN R W 0x070 ADC start0 input multiplexer GIMA output 28 0 Table 178 ADCSTART1_IN R W 0x074 ADC start1 input...

Page 311: ...ising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enable sin...

Page 312: ...nput multiplexer CAP0_3_IN address 0x400C 700C bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 Input inverted 1 EDGE Enable rising edge detection 0 0 No...

Page 313: ...1 SGPIO12 0x2 T1_CAP0 31 8 Reserved Table 154 Timer 1 CAP1_0 capture input multiplexer CAP1_0_IN address 0x400C 7010 bit description Bit Symbol Value Description Reset value Table 155 Timer 1 CAP1_1 c...

Page 314: ...ising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enable sin...

Page 315: ...capture input multiplexer CAP2_0_IN address 0x400C 7020 bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 Input inverted 1 EDGE Enable rising edge detectio...

Page 316: ...bd I2S1_RX_MWS 0x3 T2_CAP1 31 8 Reserved Table 159 Timer 2 CAP2_1 capture input multiplexer CAP2_1_IN address 0x400C 7024 bit description Bit Symbol Value Description Reset value Table 160 Timer 2 CAP...

Page 317: ...ising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enable sin...

Page 318: ...value Table 163 Timer 3 CAP3_1 capture input multiplexer CAP3_1_IN address 0x400C 7034 bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 Input inverted 1 E...

Page 319: ...CTIN_7 0x1 USART3 RX active 0x2 SOF0 Start Of Frame USB0 0x3 T3_CAP2 31 8 Reserved Table 164 Timer 3 CAP3_2 capture input multiplexer CAP3_2_IN address 0x400C 7038 bit description Bit Symbol Value De...

Page 320: ...Rising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enable si...

Page 321: ...input multiplexer CTIN_2_IN address 0x400C 7048 bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 Input inverted 1 EDGE Enable rising edge detection 0 0 N...

Page 322: ...eserved 0x3 Reserved 31 8 Reserved Table 169 SCT CTIN_3 capture input multiplexer CTIN_3_IN address 0x400C 704C bit description Bit Symbol Value Description Reset value Table 170 SCT CTIN_4 capture in...

Page 323: ...edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse generation 1 Enable single p...

Page 324: ...e Table 173 SCT CTIN_7 capture input multiplexer CTIN_7_IN address 0x400C 705C bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 Input inverted 1 EDGE Enab...

Page 325: ...Values 0xA to 0xF are reserved 0 0x0 GPIO6 28 0x1 GPIO5 3 0x2 SGPIO10 0x3 SGPIO12 0x4 Reserved 0x5 MCOB2 0x6 CTOUT_0 or T0_MAT0 0x7 CTOUT_8 or T2_MAT0 0x8 T0_MAT0 0x9 T2_MAT0 31 8 Reserved Table 174 V...

Page 326: ...14 multiplexer EVENTROUTER_14_IN address 0x400C 7068 bit description Bit Symbol Value Description Reset value 0 INV Invert input 0 0 Not inverted 1 Input inverted 1 EDGE Enable rising edge detection...

Page 327: ...put 16multiplexer EVENTROUTER_16_IN address 0x400C 706C bit description Bit Symbol Value Description Reset value Table 178 ADC start0 input multiplexer ADCSTART0_IN address 0x400C 7070 bit description...

Page 328: ...0 No edge detection 1 Rising edge detection enabled 2 SYNCH Enable synchronization 0 0 Disable synchronization 1 Enable synchronization 3 PULSE Enable single pulse generation 0 0 Disable single pulse...

Page 329: ...in interrupts must be enabled in the NVIC see Table 25 The GPIO group interrupts must be enabled in the NVIC see Table 25 GPIO port registers can be accessed by the GPDMA as memory to memory transfer...

Page 330: ...power down modes 17 3 3 GPIO port features GPIO pins can be configured as input or output by software All GPIO pins default to inputs with interrupt disabled at reset Pin registers allow pins to be se...

Page 331: ...pt block will generate an interrupt If the part is in a power savings mode it will first asynchronously wake the part up prior to asserting the interrupt request The interrupt request line can be clea...

Page 332: ...ts that are not shown are reserved Table 182 Register overview GPIO pin interrupts base address 0x4008 7000 Name Access Address offset Description Reset value Reference ISEL R W 0x000 Pin Interrupt Mo...

Page 333: ...ption Reset value Reference Table 184 Register overview GPIO GROUP1 interrupt base address 0x4008 9000 Name Access Address offset Description Reset value Reference CTRL R W 0x000 GPIO grouped interrup...

Page 334: ...128 to W159 R W 0x1200 to 0x12FC Word pin registers port 4 ext 1 word 32 bit Table 200 W160 to W191 R W 0x1280 to 0x12FC Word pin registers port 5 ext 1 word 32 bit Table 200 W192 to W223 R W 0x1300 t...

Page 335: ...x2208 Write Set register for port 2 Read output bits for port 2 0 word 32 bit Table 205 SET3 R W 0x220C Write Set register for port 3 Read output bits for port 3 0 word 32 bit Table 205 SET4 R W 0x221...

Page 336: ...abled If the pin interrupt mode is level sensitive PMODE 1 the level interrupt is enabled The IENF register configures the active level HIGH or LOW for this interrupt NOT5 WO 0x2314 Toggle port 5 NA w...

Page 337: ...el sensitive PMODE 1 the level interrupt is cleared 17 5 1 5 Pin interrupt active level falling edge interrupt enable register For each of the 8 pin interrupts selected in the PINTSELn registers see T...

Page 338: ...t in the IENF register depending on the pin interrupt mode configured in the ISEL register If the pin interrupt mode is edge sensitive PMODE 0 the falling edge interrupt is cleared If the pin interrup...

Page 339: ...level falling edge interrupt clear register CIENF address 0x4008 7018 bit description Bit Symbol Description Reset value Access 7 0 CENAF Ones written to this address clears bits in the IENF thus disa...

Page 340: ...n interrupt status register IST address 0x4008 7024 bit description Bit Symbol Description Reset value Access 7 0 PSTAT Pin interrupt status Bit n returns the status clears the edge interrupt or inver...

Page 341: ...te words to sense or set the state of four pins Remark To read the signal on the GPIO input enable the input buffer in the syscon block for the corresponding pin see Table 133 to Table 135 Table 197 G...

Page 342: ...Table 133 to Table 135 17 5 3 3 GPIO port direction registers Each GPIO port n n 0 to 7 has one direction register for configuring the port pins as inputs or outputs Table 199 GPIO port byte pin regis...

Page 343: ...corresponding MASK register and writing to one of these registers only affects output register bits that are enabled by zeros in the corresponding MASK register Table 202 GPIO port mask register MASK...

Page 344: ...f all GPIO pins except those selected for analog input or output in the I O Configuration logic A pin does not have to be selected for GPIO in I O Configuration in order to read its state There are fo...

Page 345: ...er loads the output bit with the OR of all of the bits written This feature follows the definition of truth of a multi bit value in programming languages Writing to a port s PORT register loads the ou...

Page 346: ...EL0 7 All registers in the pin interrupt block contain 8 bits corresponding to the pins called out by the PINTSEL0 7 registers The ISEL register defines whether each interrupt pin is edge or level sen...

Page 347: ...sts some recommended uses for using the GPIO port registers For initial setup after Reset or re initialization write the PORT registers To change the state of one pin write a Byte Pin or Word Pin regi...

Page 348: ...IV SGPIO outputs 10 and 12 can trigger the 12 bit ADC SGPIO outputs 14 and 15 can trigger a GPDMA request 18 3 Features Each SGPIO input output slice can be used to perform a serial to parallel or par...

Page 349: ...shifted at a time n 1 2 4 or 8 for serial dual serial quad serial and byte parallel IO Clock 12 bit counter running at SGPIO_CLOCK creates a shift clock to capture input or create output values Note t...

Page 350: ...COUNTx equals zero see Table 232 to Table 237 This interrupt is generated at each shift bit The capture clock interrupt is raised when a slice swap occurs that is at the occurrence of a capture clock...

Page 351: ...NT0 reaches 0x0 POS counts down 0 Table 222 MASK_A R W 0x0200 Mask for pattern match function of slice A 0 Table 223 MASK_H R W 0x0204 Mask for pattern match function of slice H 0 Table 224 MASK_I R W...

Page 352: ...can be done statically with register GPIO_OEREG or dynamically by another slice Table 214 indicates which slices control the output enable of which pins Note that for modes wider than 1 bit the outpu...

Page 353: ...8a 0xA dout_doutm8b 8 bit mode 8b 0xB dout_doutm8c 8 bit mode 8c 6 4 P_OE_CFG Output enable source All other values are reserved 0 R W 0x0 gpio_oe state set by GPIO_OEREG 0x4 dout_oem1 1 bit mode 0x5...

Page 354: ...multiplexing SGPIO pin Output mode register OUT_MUX_CFG bits P_OUT_CFG see Table 212 1011 1010 1001 0111 0110 0101 0011 0010 0001 0000 1000 0100 8 bit 8c 8 bit 8b 8 bit 8a 4 bit 4c 4 bit 4b 4 bit 4a 2...

Page 355: ...To avoid oscillation slices that can be a clock source for other slices cannot support external slice clocks themselves CLK_SOURCE_SLICE_MODE These slices should not feed a clock higher than SGPIO_CLO...

Page 356: ..._SLICE_MODE in this register 0x3 External SGPIO pin 8 9 10 or 11 8 7 QUALIFIER_PIN_M ODE Select qualifier pin 0 R W 0x0 SGPIO8 0x1 SGPIO9 0x2 SGPIO10 0x3 SGPIO11 10 9 QUALIFIER_ SLICE_MODE Select qual...

Page 357: ...s as shift clock the clock generated by the slice counter or by an external pin or other slice Bit INV_OUT_CLK can invert the shift clock This should only be used for external clocks coming from a pin...

Page 358: ...it Symbol Value Description Reset value Access 0 MATCH_MODE Match mode 0 R W 0x0 Do not match data 0x1 Match data 1 CLK_CAPTURE_ MODE Capture clock mode 0 R W 0x0 Use rising clock edge 0x1 Use falling...

Page 359: ...ift clock counter value If the counter has to start with a defined phase then COUNT should be set to the desired value before the counter is enabled using CTRL_ENABLE Table 218 Slice data registers RE...

Page 360: ...er MASK_A 18 6 10 Slice H mask register MASK_H 18 6 11 Slice I mask register MASK_I Table 222 Position registers POS0 to 15 addresses 0x4010 11C0 to 0x4010 11FC bit description Bit Symbol Description...

Page 361: ...slice P 0 No effect 1 Mask this bit 0 R W Table 227 GPIO input status register GPIO_INREG address 0x4010 1210 bit description Bit Symbol Description Reset value Access 15 0 GPIO_INi Bit i reflects th...

Page 362: ...e 18 6 19 Shift clock interrupt set mask register SET_EN_0 This register masks the shift clock interrupt of a slice Table 230 Slice count enable register CTRL_ENABLED address 0x4010 121C bit descripti...

Page 363: ...r CLR_EN_1 Set the CLR_EN_1 register bit to clear the corresponding bit in the ENABLE_1 register Table 234 Shift clock interrupt enable register ENABLE_0 address 0x4010 1F08 bit description Bit Symbol...

Page 364: ...dependently of the value of the corresponding ENABLE_1 bits The bits in this register can be read at any time but can only be changed by writing to the corresponding bits in the SET_STATUS_1 or CLR_ST...

Page 365: ...rupt clear status of slice n 0 W 31 16 Reserved Table 243 Exchange clock interrupt set status register SET_STATUS_1 address 0x4010 1F34 bit description Bit Symbol Description Reset value Access 15 0 S...

Page 366: ...atus of slice n 0 R 31 16 Reserved Table 248 Pattern match interrupt clear status register CLR_STATUS_2 address 0x4010 1F50 bit description Bit Symbol Description Reset value Access 15 0 CLR_STATUS_PM...

Page 367: ...fer additional features for pattern matching and processing 2 4 or 8 bit wide streams Table 252 Input interrupt enable register ENABLE_3 address 0x4010 1F68 bit description Bit Symbol Description Rese...

Page 368: ...e LSB All input data whether used as slice qualifier or clock input is synchronized this introduces a delay of one SGPIO_CLOCK cycle This latency should be taken into account when changing a pin direc...

Page 369: ...T with bit REG 0 Thus COUNT controls the serial data rate When several slices are used to create an interface port the phase between the different slices can be controlled by using different initial C...

Page 370: ...re 38 shows which slices can be concatenated Slices are ordered in four groups starting with slice A B C and D Each group consists of four concatenated slices For example the slice A input can be exte...

Page 371: ...th REG when POS reaches zero The MATCH_MODE bit must be set to 1 The input data is now compared to the programmed pattern When a match is found the pattern match interrupt is raised E external data in...

Page 372: ...e The settings are controlled by register SGPIO_MUX_CFG The 16 slices are denoted as A to P A suffix indicates which slice bit connects to a pin e g in 8 bit parallel input mode pins SGPIO0 to 7 conne...

Page 373: ...C31 K31 6 A30 C30 F30 F31 7 A31 C31 F31 L31 8 B31 B28 B30 B31 xcl xq 9 B30 B29 B31 M31 xcl xq 00 01 10 clk_qualifier qua li f i e r_ p i n _mod e 11 0 10 9 00 01 10 11 qualifier _slice A D qualifier_s...

Page 374: ...ble 256 Slice I O multiplexing x external cl clock q qualifier SGPIO Pin Input mode Parallel mode 8 bit 4 bit 2 bit 1 bit Clock Q Table 257 SGPIO applications on the LPC43xx Example Description Logic...

Page 375: ...ampled slave clock MCK is needed use a slice that is capable to create clocks for other slices D H O or P e g use slice D In slave mode MCK is an input MCK is divided down to create the shift clock fo...

Page 376: ...able 259 In Master mode the shift clocks are generated by the local slice COUNTERs The WS and CK slices contain repeating patterns and are concatenated in self loop mode The data width is 1 bit and al...

Page 377: ...r the SD and WS signals MCK is not used The slice settings that are different for slave mode 1 with SCK supplied at pin 8 are shown in Table 263 Table 261 SGPIO setting for I2S 5 1 SLICE_MUX_CFG regis...

Page 378: ...FFF FFFE The SCK pattern is static and stored in REG3 and REG_SS3 To create a SCK pattern as shown in Figure 40 set REG1 0x5555 5555 and REG_SS1 0x5555 5555 To invert the clock phase use patterns 0xAA...

Page 379: ...e an additional 2 or 4 bit input Combining the 8 and 2 or 4 bit data to single 10 or 12 bit words must be done in software From slice A and B supporting the 8 bit input mode select slice A To minimize...

Page 380: ...Eight slices are concatenated giving 8 x 32 8 32 shifts until REG need to be shadowed hence POS 0x1F The interface is started by starting slices A I E J C K F L and M by writing CTRL_ENABLE 0x1F3F Ta...

Page 381: ...s captured at a falling PIXCLK when HSYNC is low At a POS interrupt 32 data words are read from REG_SS and written to the data SRAM Then SGPIO15 is toggled to request a GP DMA transfer of 32 words fro...

Page 382: ...burst DMA request or a single DMA request The DMA burst size is set by programming the DMA Controller Memory to memory memory to peripheral peripheral to memory and peripheral to peripheral transfers...

Page 383: ...r allows peripheral to memory memory to peripheral peripheral to peripheral and memory to memory transactions Each DMA stream provides unidirectional serial DMA transfers for a single source and desti...

Page 384: ...0x1 USART0 transmit 0x2 Reserved Reserved 0x3 Reserved Reserved 2 0x0 Timer0 match 1 0x1 USART0 receive 0x2 Reserved Reserved 0x3 Reserved Reserved 3 0x0 Timer1 match 0 0x1 UART1 transmit 0x2 I2S1 DM...

Page 385: ...ilable request signals are BREQ 15 0 Burst request signals These cause a programmed burst number of data to be transferred 9 0x0 SSP0 receive SSP0 receive 0x1 I2S0 DMA request 1 0x2 SCT DMA request 1...

Page 386: ...e operation of that channel Other registers controls aspects of how source peripherals relate to the DMA Controller There are also global DMA control and status registers Table 271 Register overview G...

Page 387: ...SRCADDR3 R W 0x160 DMA Channel 3 Source Address Register 0x0000 0000 Table 286 DESTADDR3 R W 0x164 DMA Channel 3 Destination Address Register 0x0000 0000 Table 287 LLI3 R W 0x168 DMA Channel 3 Linked...

Page 388: ...Table 287 LLI7 R W 0x1E8 DMA Channel 7 Linked List Item Register 0x0000 0000 Table 288 CONTROL7 R W 0x1EC DMA Channel 7 Control Register 0x0000 0000 Table 289 CONFIG7 R W 0x1F0 DMA Channel 7 Configura...

Page 389: ...When writing to this register each data bit that is HIGH causes the corresponding bit in the status register to be cleared Data bits that are LOW have no effect on the corresponding bit in the regist...

Page 390: ...scription Bit Symbol Description Reset value Access 7 0 INTERRCLR Writing a 1 clears the error interrupt request IntErrStat for DMA channels Each bit represents one channel 0 writing 0 has no effect 1...

Page 391: ...ot used at the same time 19 6 10 DMA Software Single Request Register The SOFTSREQ Register is read write and enables DMA single transfer requests to be generated by software A DMA request can be gene...

Page 392: ...er bit A register bit is cleared when the transaction has completed Reading the register indicates which sources are requesting last single DMA transfers A request can be generated from either a perip...

Page 393: ...logic for a particular group of DMA requests This register is reset to 0 synchronization logic enabled Table 283 DMA Software Last Single Request Register SOFTLSREQ address 0x4000 202C bit description...

Page 394: ...nsferred Reading the register when the channel is active does not provide useful information This is because by the time software has processed the value read the address may have progressed It is int...

Page 395: ...s associated with it are completed Programming this register when the DMA channel is enabled may have unpredictable side effects 19 6 19 DMA channel control registers The eight read write CONTROL Regi...

Page 396: ...e value is not used if the DMA Controller is not the flow controller 0x0 R W 14 12 SBSIZE Source burst size Indicates the number of transfers that make up a source burst This value must be set to the...

Page 397: ...emark Only Master1 can access a peripheral Master0 can only access memory 0 R W 0 AHB Master 0 selected for destination transfer 1 AHB Master 1 selected for destination transfer 26 SI Source increment...

Page 398: ...00 21EC CONTROL7 bit description continued Bit Symbol Value Description Reset value Access Table 290 DMA Channel Configuration registers CONFIG 0 7 0x4000 2110 CONFIG0 to 0x4000 21F0 CONFIG7 bit descr...

Page 399: ...P1 transmit 0x4 Timer1 match 1 UART1 receive I2S1 DMA request 2 SSP1 receive 0x5 Timer2 match 0 USART2 transmit SSP1 transmit SGPIO15 0x6 Timer2 match 1 USART2 receive SSP1 receive SGPIO14 0x7 Timer3...

Page 400: ...1 receive USART3 receive 0xE ADC1 SSP1 transmit USART3 transmit 0xF DAC SCT match 3 SGPIO15 Timer3 match 0 13 11 FLOWCNTRL Flow control and transfer type This value indicates the flow controller and t...

Page 401: ...lists the bit values of the three flow control and transfer type bits identified in Table Table 290 17 A Active 0 there is no data in the FIFO of the channel 1 the channel FIFO has data This value ca...

Page 402: ...e register block stores data written or to be read across the AHB interface 19 7 1 3 DMA request and response interface See DMA Interface description for information on the DMA request and response in...

Page 403: ...ior Source endian Destination endian Source width Destination width Source transfer no byte lane Source data Destination transfer no byte lane Destination data Little Little 8 8 1 7 0 2 15 8 3 23 16 4...

Page 404: ...56 78 1 31 0 12345678 Big Big 16 8 1 31 24 1 23 16 2 15 8 2 7 0 12 34 56 78 1 31 24 2 23 16 3 15 8 4 7 0 12121212 34343434 56565656 78787878 Big Big 16 16 1 31 24 1 23 16 2 15 8 2 7 0 12 34 56 78 1 1...

Page 405: ...s the number of transfers delegated to the master interface by the lower priority channel before switching over to transfer data for the higher priority channel In the worst case this is as large as a...

Page 406: ...the channel enable bit in the relevant channel configuration register 19 8 1 5 Setting up a new DMA transfer To set up a new DMA transfer If the channel is not set aside for the DMA transaction 1 Rea...

Page 407: ...transfer has finished 2 A TC interrupt is generated if enabled 3 The DMA Controller moves on to the next LLI The following sections describe the DMA Controller data flow sequences for the four allowed...

Page 408: ...ence ends 19 8 2 2 Peripheral to peripheral DMA flow For a peripheral to peripheral DMA flow the following sequence occurs 1 Program and enable the DMA channel 2 Wait for a source DMA request 3 The DM...

Page 409: ...ority otherwise other DMA channels cannot access the bus until the memory to memory transfer has finished or other AHB masters cannot perform any transaction 19 8 3 Interrupt requests Interrupt reques...

Page 410: ...does not support AHB INCR4 or INCR8 bursts using halfword or byte transfer size Start address in SDRAM should always be aligned to a burst boundary address 19 8 4 1 Word aligned transfers across a bo...

Page 411: ...l 7 the lowest priority 3 Write the first linked list item previously written to memory to the relevant channel in the DMA Controller 4 Write the channel configuration information to the channel Confi...

Page 412: ...Source start address 0x2000 B200 Destination address set to the destination peripheral address Transfer width word 32 bit Transfer size 3072 bytes 0xC00 Fig 44 LLI example LLI 1 Source address Destina...

Page 413: ...into the DMA Controller When the first packet of data has been transferred the next LLI is automatically loaded The final LLI is stored at 0x2000 0070 and contains Source start address 0x2000 1200 Des...

Page 414: ...or CE ATA 1 1 device CRC generation and error detection Provides individual clock control to selectively turn ON or OFF clock to the card SDIO interrupts in 1 bit and 4 bit modes SDIO suspend and resu...

Page 415: ...gister Card Socket Regulators Power Switches cclk ccmd cdata Write Protect Card Detect cclk_in_drv cclk_in_sample cclk_in Host Interface Unit SDIO Interrupt Control CIU Power Pullup Card Detect Deboun...

Page 416: ...gister Table 302 CTYPE R W 0x018 Card Type Register 0 Table 303 BLKSIZ R W 0x01C Block Size Register 0x200 Table 304 BYTCNT R W 0x020 Byte Count Register 0x200 Table 305 INTMASK R W 0x024 Interrupt Ma...

Page 417: ...data FIFO More than one address is mapped to the data FIFO so that the FIFO can be accessed using bursts Table 296 Register overview SDMMC base address 0x4000 4000 Name Access Address offset Descripti...

Page 418: ...ta Used in SDIO card suspend sequence 0 0 No change 1 After suspend command is issued during read transfer software polls card to find when suspend happened Once suspend occurs software sets bit to re...

Page 419: ...VICE_ INTERRUPT _STATUS CEATA device interrupt status Software should appropriately write to this bit after power on reset or any other reset to CE ATA device After reset usually CE ATA device interru...

Page 420: ...of ff means divide by 2 255 510 and so on 0 15 8 CLK_DIVIDER1 Clock divider 1 value Clock division is 2 n For example value of 0 means divide by 2 0 0 no division bypass value of 1 means divide by 2...

Page 421: ...4000 4010 bit description Bit Symbol Description Reset value 0 CCLK_ENABLE Clock enable control for SD card clock One MMC card clock supported 0 Clock disabled 1 Clock enabled 0 15 1 Reserved 16 CCLK_...

Page 422: ...eset value 15 0 BLOCK_SIZE Block size 0x200 31 16 Reserved Table 305 Byte Count Register BYTCNT address 0x4000 4020 bit description Bit Symbol Description Reset value 31 0 BYTE_COUNT Number of bytes t...

Page 423: ...lt_switch_int Bits used to mask unwanted interrupts Value of 0 masks interrupt value of 1 enables interrupt 0 11 FRUN FIFO underrun overrun error Bits used to mask unwanted interrupts Value of 0 masks...

Page 424: ...if no data expected from card 0 0 Read from card 1 Write to card 11 TRANSFER_MODE Transfer mode Don t care if no data expected 0 0 Block data transfer command 1 Stream data transfer command 12 SEND_A...

Page 425: ...ization sequence before sending this command 20 16 Reserved Always write as 0 0 21 UPDATE_CLOCK_ REGISTERS_ONLY Update clock registers only Following register values transferred into card clock domain...

Page 426: ...the CMD line low Do NOT set disable_boot and enable_boot together 0 25 EXPECT_BOOT_ACK Expect Boot Acknowledge When Software sets this bit along with enable_boot CIU expects a boot acknowledge start p...

Page 427: ...se 0 Table 312 Response Register 3 RESP3 address 0x4000 403C bit description Bit Symbol Description Reset value 31 0 RESPONSE3 Bit 127 96 of long response 0 Table 313 Masked Interrupt Status Register...

Page 428: ...interrupt 0 masks interrupt 0 No SDIO interrupt from card 1 SDIO interrupt from card In MMC Ver3 3 only mode this bit is always 0 31 17 Reserved Table 313 Masked Interrupt Status Register MINTSTS addr...

Page 429: ...nterrupt mask status Volt_switch_int 0 11 FRUN FIFO underrun overrun error Writes to bits clear status bit Value of 1 clears status bit and value of 0 leaves bit intact Bits are logged regardless of i...

Page 430: ...d bit 14 Cmd path wait NCC 15 Wait CMD to response turnaround NOTE The command FSM state is represented using 19 bits The STATUS Register 7 4 has 4 bits to represent the command FSM states Using these...

Page 431: ...ount of status register which is 13 bits Limitation TX_WMark 1 Recommended value TX_WMARK 16 means less than or equal to FIFO_DEPTH 2 0 15 12 Reserved 0 27 16 RX_WMARK FIFO threshold watermark level w...

Page 432: ...A_WIDTH H_DATA_WIDTH Allowed combinations for MSize and TX_WMark are MSize 1 TX_WMARK 1 15 MSize 4 TX_WMark 8 MSize 4 TX_WMark 4 MSize 4 TX_WMark 12 MSize 8 TX_WMark 8 MSize 8 TX_WMark 4 Allowed combi...

Page 433: ...alue 31 0 TRANS_CARD_BYTE_ COUNT Number of bytes transferred by CIU unit to card Register should be read only after data transfer completes during data transfer register returns 0 0 Table 320 Transfer...

Page 434: ...y for dual buffer structure DSL is read write 0 7 DE SD MMC DMA Enable When set the SD MMC DMA is enabled DE is read write 10 8 PBL Programmable Burst Length These bits indicate the maximum number of...

Page 435: ...occurred IDSTS 12 10 When this bit is set the DMA disables all its bus accesses Writing a 1 clears this bit 0 3 Reserved 4 DU Descriptor Unavailable Interrupt This bit is set when the descriptor is u...

Page 436: ...ble 326 Internal DMAC Status Register IDSTS address 0x4000 408C bit description Bit Symbol Description Reset value Table 327 Internal DMAC Interrupt Enable Register IDINTEN address 0x4000 4090 bit des...

Page 437: ...h a single power supply sourcing the card slot 8 NIS Normal Interrupt Summary Enable When set a normal interrupt is enabled When reset a normal interrupt is disabled This bit enables the following bit...

Page 438: ...Transfer Type Byte Count SEND_AUTO_ STOP bit set Comments MMC Stream read 0 No Open ended stream MMC Stream read 0 Yes Auto stop after all bytes transfer MMC Stream read 0 No Open ended stream MMC St...

Page 439: ...s than 6 48 bits the data path transmits the data last in order to meet the above condition Multiple block read memory for SD card with byte count greater than 0 If the block size is less than 4 singl...

Page 440: ...a card the Data Transfer Over RINTSTS 3 interrupt occurs as soon as the data transfer from the card is over There still could be some data left in the FIFO and the RX_WMark interrupt may or may not o...

Page 441: ...lowing 1 After power on reset configure the SD MMC pins using the SFSP registers in the syscon block Table 132 2 Set masks for interrupts by clearing appropriate bits in the Interrupt Mask register 0x...

Page 442: ...KHz and use the following enumeration command sequence SD card Send CMD0 ACMD41 CMD2 CMD3 SDHC card send CMD0 SDCMD8 ACMD41 CMD2 CMD3 SDIO Send CMD5 if the function count is valid CMD3 For the SDIO me...

Page 443: ...meters Using these two registers the Module forms the command and sends it to the command bus The Module reflects the errors in the command response through the error bits of the RINTSTS register When...

Page 444: ...usy and is in a transfer state which can be done using the CMD13 and CMD7 commands respectively Table 331 CMD register settings for No Data Command Name Value Comment start_cmd 1 update_clock_ registe...

Page 445: ...ondition the Module cannot continue with data transfer The clock to the card has been stopped 5 Data read time out error bit 9 Card has not sent data within the time out period 6 Data CRC error bit 7...

Page 446: ...ment start_cmd 1 update_clock_ registers_only 0 No clock parameters update command card_number 0 Card number in use Only zero is possible because one card is support Data_expected 1 Send_initializatio...

Page 447: ...data starvation by the cpu In both cases the software should write data into the FIFO 8 When a Data_Transfer_Over interrupt is received the data command is over For an open ended block transfer if th...

Page 448: ...he Module sends the STOP command Completion of this AUTO_STOP command is reflected by the Auto_command_done interrupt A response to an AUTO_STOP is stored in the RESP1 register 0x34 A stream transfer...

Page 449: ...t Response Sequence Program the CMDARG register 0x28 with the appropriate command argument parameters listed in Table 334 Program the Command register using the command index as CMD52 Similar to the S...

Page 450: ...mand The Module then resets the data state machine and comes out of the wait state To accomplish this set abort_read_data bit 8 in the Control register Wait for data completion Get pending bytes to tr...

Page 451: ...sfer commands For information on the basic settings and interrupts generated for different conditions refer to Data Transfer Commands 20 7 5 2 1 Reset and Device Recovery Before starting CE ATA operat...

Page 452: ...nd involves data transfer between the CE ATA device and the Module To send a data command the Module needs a command argument total data size and block size Software can receive or send data through t...

Page 453: ...pected Read_ceata_device 0 1 1 If RW_BLK or RW_REG read update_clock_ registers_only 0 No clock parameters update command card_number 0 Card number in use Only zero is possible because one card is sup...

Page 454: ...r 0 read 30 24 Reserved 0 23 16 Reserved 0 15 8 Data Count Unit 15 8 Data count 1 0 Data Count Unit 7 0 Data count Table 341 CMD register settings Name Value Comment start_cmd 1 Css_expect 1 Command C...

Page 455: ...out happened while waiting for Command Completion Signal CCS the cpu needs to send Command Completion Signal Disable CCSD followed by a STOP command to abort the pending ATA command The cpu can progra...

Page 456: ...to 0 BLKSIZ register bits 15 0 and BYTCNT register Set to 16 The cpu controller uses the following settings for data retrieval RW_BLK CMD register settings ccs_expect set to 1 data_expected set to 1...

Page 457: ...elds of the task file cleared to 0 BLKSIZ register bits 15 0 and BYTCNT register Set to 16 20 7 5 3 Controller DMA FIFO Reset Usage Communication with the card involves the following Controller Contro...

Page 458: ...retry the whole data transfer again or retry from a specified block onwards By reading the contents of the TCBCNT later the software can decide how many bytes remain to be copied Response errors Set w...

Page 459: ...a transfer if a negative CRC status is received from the device the data path signals a data CRC error to the BIU by setting the data CRC error bit in the RINTSTS register It then continues further da...

Page 460: ...IDSTS for the data that ends in the buffer pointed to by this descriptor 2 LD Last Descriptor When set this bit indicates that the buffers pointed to by this descriptor are the last buffers of the dat...

Page 461: ...that the descriptor is owned by the SD MMC DMA When this bit is reset it indicates that the descriptor is owned by the Host The SD MMC DMA clears this bit when it completes the data transfer Table 344...

Page 462: ...t address and the number of transfers required to the AHB Master Interface When the AHB Interface is configured for fixed length bursts then it transfers data using the best combination of INCR4 8 16...

Page 463: ...essed using a burst SINGLE transfers are performed on AHB Master Interface 8 The SD MMC DMA fetches the Transmit data from the data buffer in the Host memory and transfers to the FIFO for transmission...

Page 464: ...ng a 1 to the corresponding bit position When all the enabled interrupts within a group are cleared the corresponding summary bit is cleared When both the summary bits are cleared the interrupt signal...

Page 465: ...rflow underflow can result For example consider the following scenarios For transmit PBL 4 Tx watermark 1 For these programming values if the FIFO has only one location empty it issues a dw_dma_req to...

Page 466: ...1 in all four SFSCLKn registers in the SCU The EMC is reset by the EMC_RST reset 21 UM10503 Chapter 21 LPC43xx External Memory Controller EMC Rev 1 3 6 July 2012 User manual Table 349 EMC pinout for d...

Page 467: ...naround delay Output enable and write enable delays Extended wait 16 bit and 32 bit wide chip select SDRAM memory support with up to four chip selects and up to 256 MB of data Controller supports 2 kb...

Page 468: ...The LPC43xx External Memory Controller EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM ROM and Flash as well as dynam...

Page 469: ...shows the address ranges of the chip selects Fig 49 EMC block diagram SRAM EMC_A 23 0 EMC_WE EMC_D 31 0 write MEMORY CONTROLLER STATE MACHINE AHB SLAVE REGISTER INTERFACE AHB SLAVE MEMORY INTERFACE E...

Page 470: ...DRAM clock enable signals EMC_CLK 3 0 EMC_CLK01 EMC_CLK23 O SDRAM clock signals EMC_DQMOUT 3 0 O Data mask output to SDRAM memory banks EMC_DYCS 3 0 O SDRAM memory bank select EMC_CAS O Column address...

Page 471: ...de register to active command time 0xF 0xF Table 370 R W 0x05C 0x07C Reserved STATICEXTENDEDWAIT R W 0x080 Selects time for long static memory read and write transfers 0 0 Table 371 R W Reserved DYNAM...

Page 472: ...R W 0x218 Selects the number of bus turnaround cycles for chip select 0 0xF 0xF Table 381 0x21C Reserved STATICCONFIG1 R W 0x220 Selects the memory configuration for static chip select 1 0 0 Table 375...

Page 473: ...ts the delay from chip select 2 to a write access 0x1F 0x1F Table 380 STATICWAITTURN2 R W 0x258 Selects the number of bus turnaround cycles for chip select 2 0xF 0xF Table 381 0x25C Reserved STATICCON...

Page 474: ...h CS0 and DYCS0 memory areas Clearing the M bit enables CS0 and DYCS0 memory to be accessed 1 0 Normal memory map 1 Reset memory map Static memory CS1 is mirrored onto CS0 and DYCS0 POR reset value 2...

Page 475: ...erved bits The value read from a reserved bit is not defined Table 355 EMC Status register STATUS address 0x4000 5004 bit description Bit Symbol Value Description Reset value Table 356 EMC Configurati...

Page 476: ...s LOW the output clock CLKOUT is stopped when there are no SDRAM transactions The clock is also stopped during self refresh mode 1 0 CLKOUT stops when all SDRAMs are idle and during self refresh mode...

Page 477: ...ions when the auto refresh command is issued depending on the status of the memory controller 21 7 6 Dynamic Memory Read Configuration register The DYNAMICREADCONFIG register configures the dynamic me...

Page 478: ...s register is used for all four dynamic memory chip selects Therefore the worst case value for all of the chip selects must be programmed Table 359 Dynamic Memory Read Configuration register DYNAMICRE...

Page 479: ...with one wait state Note This register is used for all four dynamic memory chip selects Therefore the worst case value for all of the chip selects must be programmed 21 7 11 Dynamic Memory Data In to...

Page 480: ...or disabled mode This value is normally found in SDRAM data sheets as tRC This register is accessed with one wait state Note This register is used for all four dynamic memory chip selects Therefore t...

Page 481: ...data sheets as tXSR This register is accessed with one wait state Note This register is used for all four dynamic memory chip selects Therefore the worst case value for all of the chip selects must be...

Page 482: ...n or when there are no current or outstanding transactions However if necessary these control bits can be altered during normal operation This register is accessed with one wait state Table 369 Dynami...

Page 483: ...x4000 5120 DYNAMICCONFIG1 0x4000 5140 DYNAMICCONFIG2 0x4000 5160 DYNAMICCONFIG3 bit description Bit Symbol Value Description Reset value 2 0 Reserved user software should not write ones to reserved bi...

Page 484: ...1 01 64 Mb 4Mx16 4 banks row length 12 column length 8 0 1 010 00 128 Mb 16Mx8 4 banks row length 12 column length 10 0 1 010 01 128 Mb 8Mx16 4 banks row length 12 column length 9 0 1 011 00 256 Mb 32...

Page 485: ...nable you to program the RAS and CAS latencies for the relevant dynamic memory It is recommended that these registers are modified during system initialization or when there are no current or outstand...

Page 486: ...0 5164 DYNAMICRASCAS3 bit description Bit Symbol Value Description Reset value 1 0 RAS RAS latency active to read write delay 11 0x0 Reserved 0x1 One CCLK cycle 0x2 Two CCLK cycles 0x3 Three CCLK cycl...

Page 487: ...the BLSn 3 0 signals connected to the UBn and LBn upper byte and lower byte signals in the static memory In this case a write to a particular byte must assert the appropriate UBn or LBn signal LOW Fo...

Page 488: ...ied during system initialization or when there are no current or outstanding transactions This can be ensured by waiting until the EMC is idle and then entering low power or disabled mode These regist...

Page 489: ...ting until the EMC is idle and then entering low power or disabled mode This register is accessed with one wait state Table 377 Static Memory Output Enable delay registers STATICWAITOEN 0 3 address 0x...

Page 490: ...state Table 379 Static Memory Page Mode Read Delay registers STATICWAITPAGE 0 3 address 0x4000 5210 STATICWAITPAGE0 0x4000 5230 STATICWAITPAGE1 0x4000 5250 STATICWAITPAGE2 0x4000 5270 STATICWAITPAGE3...

Page 491: ...same memory bank between read and write to different memory banks Bus turn around cycles prevent bus contention on the external memory data bus Table 381 Static Memory Turn Round Delay registers STAT...

Page 492: ...f endianness problems all data transfers to and from the registers of the EMC must be 32 bits wide Note If an access is attempted with a size other than a word 32 bits it causes an ERROR response to t...

Page 493: ...d to Merge write transactions so that the number of external transactions are minimized Buffer data until the EMC can complete the write transaction improving AHB write latency Convert all dynamic mem...

Page 494: ...ffer the LRU buffer is selected If the buffer is dirty contains write data the write data is flushed to memory When an empty buffer is available the read command is posted to the memory A buffer fille...

Page 495: ...s the mode register with the correct settings Table 382 SDRAM mode register description Address line SDRAM mode register bit Value Description A2 A0 2 0 Burst length 000 1 M3 0 1 M3 1 001 2 M3 0 2 M3...

Page 496: ...er of banks Most SDRAM devices use 2 bank select bits for four banks Select the SDRAM memory mapped address DYCSX The SDRAM read address is ADDRESS DYCSX MODE OFFSET 21 8 5 2 1 Example for setting the...

Page 497: ...on is accomplished using the SYSCON registers Symbol a_b in the following figures refers to the highest order address line in the data bus Symbol a_m refers to the highest order address line of the me...

Page 498: ...erfaced to one 8 bit memory chip Fig 50 32 bit bank external memory interfaces bits MW 10 OE CS WE CE OE WE B3 B2 B1 B0 IO 31 0 A a_m 0 D 31 0 BLS 2 A a_b 2 BLS 3 BLS 0 BLS 1 a 16 bit wide memory bank...

Page 499: ...2012 All rights reserved User manual Rev 1 3 6 July 2012 499 of 1269 NXP Semiconductors UM10503 Chapter 21 LPC43xx External Memory Controller EMC 21 8 6 3 8 bit wide memory bank connection Fig 52 8 bi...

Page 500: ...r library available on the LPCware web site 22 4 General description The SPI Flash Interface SPIFI allows low cost serial flash memories to be connected to the Cortex M4 processor with little performa...

Page 501: ...mory space In practice the usable space is limited to the size of the connected device Table 385 SPIFI Pin description Pin function Direction Description SPIFI_SCK O Serial clock for the flash memory...

Page 502: ...5LD010 Pm25LD020 Pm25LD040 Pm25LQ032 Elite ESMT F25L08P F25L16P F25L32P F25L32Q Eon EN25F10 EN25F20 EN25F40 EN25Q40 EN25F80 EN25Q80 EN25QH16 EN25Q32 EN25Q64 EN25Q128 Gigadevice GD25Q512 GD25Q10 GD25Q2...

Page 503: ...ontroller enable the PHY in the CREG0 register bit 5 The SOF VF indicator can be connected to Timer3 or the to SCT through the GIMA see Section 23 7 7 and Table 148 The registers for frame length adju...

Page 504: ...s of devices to each other in order to exchange data or for other purposes Many portable devices can benefit from the ability to communicate to each other over the USB interface without intervention o...

Page 505: ...e Maximum Packet Size see Table 390 is dependent on the type of endpoint and the device configuration low speed full speed or high speed Table 388 USB related acronyms Acronym Description ATX Analog T...

Page 506: ...ption USB0_IND0 O Port indicator LED control output USB0_IND1 O Port indicator LED control output USB0_PWR_FAULT I Port power fault signal indicating overcurrent condition this signal monitors over cu...

Page 507: ...ut is only 5 V tolerant when VDDIO is present USB0_ID I Indicates to the transceiver whether connected as an A device USB0_ID LOW or B device USB0_ID HIGH For OTG this pin has an internal pull up resi...

Page 508: ...ndex device mode 0 0x0000 1F20 Table 406 FRINDEX_H R W 0x14C USB frame index host mode 0 Table 407 0x150 Reserved DEVICEADDR R W 0x154 USB device address device mode 0 0x0400 0000 Table 409 PERIODICLI...

Page 509: ...ice mode 0 0xA Table 423 USBMODE_H R W 0x1A8 USB device mode host mode 0 Table 424 Device endpoint registers ENDPTSETUPSTAT R W 0x1AC Endpoint setup status 0 0 Table 425 ENDPTPRIME R W 0x1B0 Endpoint...

Page 510: ...ss 7 0 CAPLENGTH Indicates offset to add to the register base address at the beginning of the Operational Register 0x40 RO 23 8 HCIVERSION BCD encoding of the EHCI revision number supported by this ho...

Page 511: ...st must always be aligned on a 4K boundary This requirement ensures that the frame list is always physically contiguous 1 RO 2 ASP Asynchronous Schedule Park Capability If this bit is set to a one the...

Page 512: ...high speed mode Software should use this bit to prevent an attach event before the device controller has been properly initialized 1 RST Controller reset Software uses this bit to reset the controlle...

Page 513: ...nized R W 0 15 Not used in device mode 23 16 ITC Interrupt threshold control The system software uses this field to set the maximum rate at which the host device controller will issue interrupts ITC c...

Page 514: ...cess the periodic schedule 1 Use the PERIODICLISTBASE register to access the periodic schedule 5 ASE This bit controls whether the host controller skips processing the asynchronous schedule R W 0 0 Do...

Page 515: ...le 401 0 23 16 ITC Interrupt threshold control The system software uses this field to set the maximum rate at which the host device controller will issue interrupts ITC contains the maximum interrupt...

Page 516: ...rror interrupt 0 R WC 0 This bit is cleared by software writing a one to it 1 When completion of a USB transaction results in an error condition this bit is set by the host device controller This bit...

Page 517: ...DCSuspend 0 R WC 0 The device controller clears the bit upon exiting from a Suspended state This bit is cleared by software writing a one to it 1 When a device controller enters a Suspended state from...

Page 518: ...ting a one to it 1 The Host Controller sets this bit to a one when on any port a Connect Status occurs a Port Enable Disable Change occurs or the Force Port Resume bit is set as the result of a J K tr...

Page 519: ...chronous Schedule Enable bit in the USBCMD register When this bit and the Asynchronous Schedule Enable bit are the same value the Asynchronous Schedule is either enabled if both are 1 or disabled if b...

Page 520: ...upt threshold The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register 0 R W 2 PCE Port change detect enable When this bit is a one and the Port Change Detect bit in...

Page 521: ...the USBSTS register is a one the host controller will issue an interrupt The interrupt is acknowledged by software clearing the Frame List Rollover bit 4 Reserved 0 5 AAE Interrupt on asynchronous adv...

Page 522: ...depends on the size of the frame list as set by system software in the Frame List Size field in the USBCMD register This register must be written as a DWord Byte writes produce undefined results This...

Page 523: ...8 elements 32 bytes 5 Table 408 Number of bits used for the frame list index USBCMD bit 15 USBCMD bit 3 USBCMD bit 2 Frame list size N Table 409 USB Device Address register in device mode DEVICEADDR a...

Page 524: ...t asynchronous queue head to be executed by the host Bits 4 0 of this register cannot be modified by the system software and will always return a zero when read 23 6 9 TT Control register TTCTRL 23 6...

Page 525: ...ncy FIFO before moving the data onto the USB bus The specific areas of performance include the how much data to post into the FIFO and an estimate for how long that operation should take in the target...

Page 526: ...ion Bit Symbol Description Reset value Access 7 0 TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet be...

Page 527: ...in the EPTNE and EPRNE field respectively Table 416 USB BINTERVAL register BINTERVAL address 0x4000 6174 bit description Bit Symbol Description Reset value Access 3 0 BINT bInterval value see Section...

Page 528: ...orresponds to endpoint 5 Bit 1 corresponds to endpoint 1 Bit 0 corresponds to endpoint 0 0x00 R W 15 6 Reserved 21 16 EPTNE Tx endpoint NAK Each bit enables the corresponding TX NAK bit If this bit is...

Page 529: ...esume detected driven on port 7 SUSP Suspend In device mode this is a read only status bit 0 RO 0 Port not in Suspended state 1 Port in Suspended state 8 PR Port reset In device mode this is a read on...

Page 530: ...always 0 in device mode 0 23 PHCD PHY low power suspend clock disable PLPSCD In device mode The PHY can be put into Low Power Suspend Clock Disable when the device is not running USBCMD Run Stop 0 or...

Page 531: ...e is present on the port 1 CSC Connect status change Indicates a change has occurred in the port s Current Connect Status The host device controller sets this bit for all changes to the port device co...

Page 532: ...one to drive resume signaling The Host Controller sets this bit to one if a J to K transition is detected while the port is in the Suspended state When this bit transitions to a one because a J to K t...

Page 533: ...in suspending a port if there is a transaction currently in progress on the USB 8 PR Port reset When software writes a one to this bit the bus reset sequence as defined in the USB Specification Revisi...

Page 534: ...the port is operating in test mode The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the test mode support specified in the EHCI specification Writing the PTC field to any of the FORCE_ENABLE_...

Page 535: ...the PHY clock enabled 1 Writing a 1 disables the PHY clock Reading a 1 indicates the status of the PHY clock disabled 24 PFSC Port force full speed connect 0 R W 0 Port connects at any speed 1 Writing...

Page 536: ...n the OTG controller is in device mode This controls the pull down on USB_DM 0 R W 4 DP Data pulsing Setting this bit to 1 causes the pull up on USB_DP to be asserted for data pulsing during SRP 0 R W...

Page 537: ...session end threshold Software must write a 1 to this bit to clear it 0 R WC 21 ms1S 1 millisecond timer interrupt status This bit is set once every millisecond Software must write a 1 to this bit to...

Page 538: ...scription Reset value Access 1 0 CM1_0 Controller mode The controller defaults to an idle state and needs to be initialized to the desired operating mode after reset This register can only be written...

Page 539: ...BMODE_D address 0x4000 61A8 bit description continued Bit Symbol Value Description Reset value Access Table 424 USB Mode register in host mode USBMODE_H address 0x4000 61A8 bit description Bit Symbol...

Page 540: ...width systems where the RX and TX buffers are sufficient to contain the entire packet Enabling stream disable also has the effect of ensuring the the TX latency is filled to capacity before the packet...

Page 541: ...r descriptor to an endpoint Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer Hardware will clear this bit when t...

Page 542: ...ter indicates that a received transmit event occurred and software should read the corresponding endpoint queue to determine the transfer status If the corresponding IOC bit is set in the Transfer Des...

Page 543: ...Endpoint transmit complete event for physical IN endpoints 5 to 0 This bit is set to 1 by hardware when a transmit event IN INTERRUPT occurred ETCE0 endpoint 0 ETCE5 endpoint 5 0 R WC 31 22 Reserved...

Page 544: ...t ok 1 Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host It will continue returning STALL until the bit is cleared by software or it w...

Page 545: ...en the host and device 0 WS 7 RXE Rx endpoint enable Remark An endpoint should be enabled only after it has been configured 0 R W 0 Endpoint disabled 1 Endpoint enabled 15 8 Reserved 16 TXS Tx endpoin...

Page 546: ...a minimum of 133 ns 4 30 MHz clock cycles in duration to reset all logic correctly The ATX_RGEN module generates a reset signal towards the ATX fulfilling above 3 requirements no matter how the AHB re...

Page 547: ...n 23 1 for connecting the SOF signal to other peripherals on the LPC43xx The USB OTG generates a SOF VF indicator signal which can be used by user specific external logic In FS mode the SOF VF indicat...

Page 548: ...of the connect event and starts the reset Software will still receive notification of the connect event CCS bit in the PORTSC register but should not write the reset bit in the USBCMD register when t...

Page 549: ...few microseconds after connect will require at a minimum 50 ms this is the time for which the DCD must be ready to accept setup packets after having received notification that the reset has been dete...

Page 550: ...operation and when the host and device negotiate a High Speed connection i e Chirp completes successfully Since this controller has an embedded Transaction Translator the port enable will always be s...

Page 551: ...nslator see USB 2 0 specification and for the EHCI controller moving packets between system memory and a USB HS hub Since the embedded Transaction Translator exists within the host controller there is...

Page 552: ...3 Sequencing is provided a packet length estimator ensures no full speed low speed packet babbles into SOF time 2 USB 2 0 specification section 11 17 4 Transaction tracking for 2 data pipes 3 USB 2 0...

Page 553: ...sses in the capability registers and operational register are used in device mode For read and write operations to these register note the following Always write zero to all EHCI reserved fields some...

Page 554: ...re assign the port owner for any device that does not connect at High Speed this host controller supports direct attach of non High Speed devices Therefore the following differences are important rega...

Page 555: ...y 23 9 1 Endpoint queue head dQH The device Endpoint Queue Head dQH is where all transfers are managed The dQH is a 48 byte data structure but must be aligned on 64 byte boundaries During priming of a...

Page 556: ...this information while the corresponding endpoint is enabled Fig 56 Endpoint queue head data structure ENDPOINT CAPABILITIES CHARACTERISTICS BUFFER POINTER PAGE 0 BUFFER POINTER PAGE 1 BUFFER POINTER...

Page 557: ...ere N is computed using Max_packet_length and the Total_bytes field in the dTD 01 Execute one transaction 10 Execute two transactions 11 Execute three transactions Remark Non isochronous endpoints mus...

Page 558: ...escriptor dTD The dTD describes to the device controller the location and quantity of data to be sent received for a given transfer The DCD should not attempt to modify any field in an active dTD exce...

Page 559: ...rs can access Although it is possible to create a transfer up to 20 kB this assumes that the first offset into the first page is zero When the offset cannot be predetermined crossing past the fifth pa...

Page 560: ...in the dTD 01 Execute one transaction 10 Execute two transactions 11 Execute three transactions Remark Non ISO and Non TX endpoints must set MultO 00 9 8 reserved R W 7 0 Status Status This field is u...

Page 561: ...it is necessary to have the queue heads setup for endpoint zero before the device attach occurs Shortly after the device is enabled a USB reset will occur followed by a setup packet arriving at endpo...

Page 562: ...e Powered state A transition from the Powered state to the Attached state occurs when the Run Stop bit is set to a 1 After receiving a reset on the bus the port will enter the defaultFS or defaultHS s...

Page 563: ...ble is set After a reset is received all endpoints except endpoint 0 are disabled and any primed transactions will be cancelled by the device controller The concept of priming will be clarified below...

Page 564: ...mode when there is bus activity A USB device may also request the host to exit suspend mode or selective suspend by using electrical signaling to indicate remote wake up The ability of a device to sig...

Page 565: ...each direction For example the DCD can configure endpoint 1 IN to be a bulk endpoint and endpoint 1 OUT to be an isochronous endpoint This helps to conserve the total number of endpoints required for...

Page 566: ...ed by the device controller at the start of a new control transaction setup phase When enabling a protocol stall the DCD should enable the stall bits both directions as a pair A single write to the EN...

Page 567: ...ted in the USB 2 0 Specification At USB 1 1 Full or Low Speed rates this turnaround time was significant and the USB 1 1 device controllers were designed so that the device controller could access mai...

Page 568: ...identical to priming of transmit endpoints from the point of view of the DCD At the device controller the major difference in the operational model is that there is no data movement of the leading pac...

Page 569: ...cessful completion of the packets described by the dTD the active bit in the dTD will be cleared and the next pointer will be followed when the Terminate bit is clear When the Terminate bit is set the...

Page 570: ...terrupt and inspecting USBMODE to determine that a setup packet was received on a particular pipe 1 Duplicate contents of dQH SetupBuffer into local software byte array 2 Write 1 to clear correspondin...

Page 571: ...new setup packet the status and or handshake phases may still be pending from a previous control sequence These should be flushed deallocated before linking a new status and or handshake dTD for the m...

Page 572: ...y sized and the DCD is responsive 23 10 9 Isochronous endpoint operational model Isochronous endpoints are used for real time scheduled delivery of data and their operational model is significantly di...

Page 573: ...t in the status field indicates a fulfillment error condition When a fulfillment error occurs the device controller will force retire the ISO dTD and move to the next ISO dTD It is important to note t...

Page 574: ...a specific micro frame number N the DCD should interrupt on SOF during frame N 1 When the FRINDEX N 1 the DCD must write the prime bit The device controller will prime the isochronous endpoint in mic...

Page 575: ...and the dTD overlay examined in section Section 23 10 6 the dQH also contains the following parameters for the associated endpoint Multiplier Maximum Packet Length Interrupt On Setup The complete init...

Page 576: ...dge has occurred the DCD must not attempt to access the setup buffer in the dQH RX Only the local software copy should be examined 3 Check for pending data or status dTD s from previous control transf...

Page 577: ...bit set to 1 and all remaining status bits set to 0 6 Fill in buffer pointer page 0 and the current offset to point to the start of the data buffer 7 Initialize buffer pointer page 1 through page 4 t...

Page 578: ...nterrupt On Complete bit was set or alternately the DCD can poll the endpoint complete register to find when the dTD had been executed After a dTD has been executed DCD can check the status bits to de...

Page 579: ...ENDPTFLUSH A safeguard is in place to refuse the flush to ensure that the packet in progress completes successfully The DCD may need to repeatedly flush any endpoints that fail to flush by repeating...

Page 580: ...s Error interrupts will be least frequent and should be placed last in the interrupt service routine Table 448 High frequency interrupt events Execution order Interrupt Action 1a USB interrupt ENDPTSE...

Page 581: ...t can be generated which is controlled by the port change Detect Enable bit in the USBINTR control register Software then has 7 ms to transition a bus powered device into the Suspended state In the Su...

Page 582: ...result of a suspend command from the host Suspend is signaled on the bus by 3 ms of idle time on the bus This will generate a suspend interrupt to the software at which point the software must prepar...

Page 583: ...a true suspend command issued by host 23 11 3 Host power states From an operational state when a host gets a low power request it must set the suspend bit in the port controller This will put an idle...

Page 584: ...ter see Table 29 Software should check for this signal to be HIGH before stopping the USB PLL and putting the chip in low power mode Note that the event router block doesn t support a raw pin status r...

Page 585: ...controller a change on vbusvalid occurs VBUS threshold at 4 4 V is crossed a change on bvalid occurs VBUS threshold at 4 0 V is crossed The vbusvalid and bvalid signals coming from the transceiver ar...

Page 586: ...EG block see Table 56 parts with on chip flash only 24 2 1 Full speed mode without external PHY In Full speed mode use CLK_USB1 to generate a clock for the USB1 interface 24 2 2 High speed mode with U...

Page 587: ...neral description The USB1 controller provides plug and play connection of peripheral devices to a host with three different data speeds High Speed with a data rate of 480 Mbps with external PHY only...

Page 588: ...is pull up is enabled when software sets the RS bit Bit 0 in the USBCMD register The USB1 controller checks whether the USB1_VBUS pin is pulled HIGH there is no voltage monitoring For applications whi...

Page 589: ...B1 pin description Pin function Direction Description Table 453 Register access abbreviations Abbreviation Description R W Read Write R WC Read Write one to Clear R WO Read Write Once RO Read Only WO...

Page 590: ...le 477 BINTERVAL R W 0x174 Length of virtual frame 0x0000 0000 Table 478 ENDPTNAK R W 0x178 Endpoint NAK device mode 0x0000 0000 Table 479 ENDPTNAKEN R W 0x17C Endpoint NAK Enable device mode 0x0000 0...

Page 591: ...eam ports implemented on this host controller 0x1 RO 4 PPC Port Power Control This field indicates whether the host controller implementation includes port power control 0x1 RO 7 5 These bits are rese...

Page 592: ...speed queue heads in the Asynchronous Schedule The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mod...

Page 593: ...state is not recommended since the effect on an attached host is undefined In order to ensure that the device is not in an attached state before initiating a device controller reset all primed endpoin...

Page 594: ...e transaction and has entered the stopped state Software should not write a one to this field unless the host controller is in the Halted state i e HCHalted in the USBSTS register is a one 1 When set...

Page 595: ...doorbell When the host controller has evicted all appropriate cached schedule states it sets the Interrupt on Async Advance status bit in the USBSTS register If the Interrupt on Sync Advance Enable bi...

Page 596: ...set the maximum rate at which the host device controller will issue interrupts ITC contains the maximum interrupt interval measured in micro frames Valid values are shown below All other values are r...

Page 597: ...rror interrupt 0 R WC 0 This bit is cleared by software writing a one to it 1 When completion of a USB transaction results in an error condition this bit is set by the Host Device Controller This bit...

Page 598: ...uspend 0 R WC 0 The device controller clears the bit upon exiting from a Suspended state This bit is cleared by software writing a one to it 1 When a device controller enters a Suspended state from an...

Page 599: ...g a one to it 1 The Host Controller sets this bit to a one when on any port a Connect Status occurs a Port Enable Disable Change occurs or the Force Port Resume bit is set as the result of a J K trans...

Page 600: ...s Schedule Enable bit in the USBCMD register When this bit and the Asynchronous Schedule Enable bit are the same value the Asynchronous Schedule is either enabled if both are 1 or disabled if both are...

Page 601: ...eshold The interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS register 0 R W 2 PCE Port change detect enable When this bit is a one and the Port Change Detect bit in the US...

Page 602: ...e USBSTS register is a one the host controller will issue an interrupt The interrupt is acknowledged by software clearing the Frame List Rollover bit 4 Reserved 0 5 AAE Interrupt on asynchronous advan...

Page 603: ...size of the frame list as set by system software in the Frame List Size field in the USBCMD register This register must be written as a DWord Byte writes produce undefined results This register canno...

Page 604: ...Table 469 Number of bits used for the frame list index USBCMD bit 15 USBCMD bit 3 USBCMD bit 2 Frame list size Size of FRINDEX12_3 bit field Table 470 USB Device Address register in device mode DEVICE...

Page 605: ...host Bits 4 0 of this register cannot be modified by the system software and will always return a zero when read 24 6 8 TT Control register TTCTRL 24 6 8 1 Device mode This register is not used in de...

Page 606: ...FIFO before moving the data onto the USB bus The specific areas of performance include the how much data to post into the FIFO and an estimate for how long that operation should take in the target sys...

Page 607: ...Description Reset value Access 7 0 TXSCHOH FIFO burst threshold This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the...

Page 608: ...on is performed To execute a wakeup operation write all 32 bits of the ULPI Viewport where ULPIPORT is constructed appropriately and the ULPIWU bit is a 1 and ULPIRUN bit is a 0 Poll the ULPI Viewport...

Page 609: ...nning a read or write operation R W 0 0 Read 1 Write 30 ULPIRUN ULPI Read Write Run Writing the 1 to this bit will begin the read write operation The bit will automatically transition to 0 after the r...

Page 610: ...9 USB endpoint NAK register in device mode ENDPTNAK address 0x4000 7178 bit description Bit Symbol Description Reset value Access 3 0 EPRN Rx endpoint NAK Each RX endpoint has one bit in this field Th...

Page 611: ...K bit is set the NAK interrupt bit is set Bit 3 corresponds to endpoint 3 Bit 1 corresponds to endpoint 1 Bit 0 corresponds to endpoint 0 0x00 R W 15 4 Reserved 19 16 EPTNE Tx endpoint NAK Each bit en...

Page 612: ...resume K state detected driven on port 1 Resume detected driven on port 7 SUSP Suspend In device mode this is a read only status bit 0 RO 0 Port not in Suspended state 1 Port in Suspended state 8 PR...

Page 613: ...isable PLPSCD In device mode The PHY can be put into Low Power Suspend Clock Disable when the device is not running USBCMD Run Stop 0 or the host has signaled suspend PORTSC SUSPEND 1 Low power suspen...

Page 614: ...is present on the port 1 CSC Connect status change Indicates a change has occurred in the port s Current Connect Status The host device controller sets this bit for all changes to the port device conn...

Page 615: ...drive resume signaling The Host Controller sets this bit to one if a J to K transition is detected while the port is in the Suspended state When this bit transitions to a one because a J to K transit...

Page 616: ...nd that there may be a delay in suspending a port if there is a transaction currently in progress on the USB 8 PR Port reset When software writes a one to this bit the bus reset sequence as defined in...

Page 617: ...are off 0x1 Amber 0x2 Green 0x3 Undefined 19 16 PTC3_0 Port test control Any value other than 0000 indicates that the port is operating in test mode The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensi...

Page 618: ...PHY clock Reading a 0 indicates the status of the PHY clock enabled 1 Writing a 1 disables the PHY clock Reading a 1 indicates the status of the PHY clock disabled 24 PFSC Port force full speed connec...

Page 619: ...mode after reset This register can only be written once after reset If it is necessary to switch modes software must reset the controller by writing to the RESET bit in the USBCMD register before repr...

Page 620: ...E_D address 0x4000 71A8 bit description continued Bit Symbol Value Description Reset value Access Table 485 USB Mode register in host mode USBMODE_H address 0x4000 71A8 bit description Bit Symbol Valu...

Page 621: ...andwidth systems where the RX and TX buffers are sufficient to contain the entire packet Enabling stream disable also has the effect of ensuring the TX latency is filled to capacity before the packet...

Page 622: ...fer descriptor to an endpoint Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer Hardware will clear this bit when...

Page 623: ...register indicates that a received transmit event occurred and software should read the corresponding endpoint queue to determine the transfer status If the corresponding IOC bit is set in the Transfe...

Page 624: ...dpoint transmit complete event for physical IN endpoints This bit is set to 1 by hardware when a transmit event IN INTERRUPT occurred ETCE0 endpoint 0 ETCE3 endpoint 3 0 R WC 31 20 Reserved Table 491...

Page 625: ...1 Endpoint stalled Software can write a one to this bit to force the endpoint to return a STALL handshake to the Host It will continue returning STALL until the bit is cleared by software or it will...

Page 626: ...the host and device 0 WS 7 RXE Rx endpoint enable Remark An endpoint should be enabled only after it has been configured 0 R W 0 Endpoint disabled 1 Endpoint enabled 15 8 Reserved 16 TXS Tx endpoint...

Page 627: ...ignal For USB1 this signal is not connected to any register The SUSP_CTRL module also generates an output signal indicating whether the AHB clock is needed or not If not the AHB clock is allowed to be...

Page 628: ...ware clears the PORTSC1 PHCD bit a device is connected and the PORTSC1 WKCN bit is set a device is disconnected an the PORTSC1 WKDC bit is set an over current condition occurs and the PORTSC1 WKOC bit...

Page 629: ...y the required interface needed to interface with Devices using the USB CDC ACM Class Communication Device Class function driver initialization parameter data structure Table 519 USBD_CDC_API class st...

Page 630: ..._INIT_PARAM class structure HID class API functions structure This structure contains pointers to all the functions exposed by the HID function driver module Table 526 USBD_HW_API class structure USB...

Page 631: ...Ptr to USB ROM Driver table Ptr to Device Table 2 Reserved Ptr to Device Table 1 Ptr to USB ROM Driver table hw core dfu Ptr to Function 2 Ptr to Function 0 Ptr to Function 1 Ptr to Function n USB API...

Page 632: ...scriptorType bDescriptorSubtype uint8_tuint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR bDescriptorSubtype bmCapabilities uint8_tuint8_t _CDC_ABSTRACT_CONTROL_MANAGEMENT_DESCRIPTOR bmCapabilities T...

Page 633: ...Table 499 _CDC_UNION_1SLAVE_DESCRIPTOR class structure Member Description sUnion CDC_UNION_DESCRIPTORCDC_UNION_DESCRIPTOR _CDC_UNION_1SLAVE_DESCRIPTOR sUnion bSlaveInterfaces uint8_tuint8_t _CDC_UNIO...

Page 634: ..._HID_DESCRIPTOR _HID_DESCRIPTOR_LISTPRE_PACK struct POST_PACK _HID_DESCRIPTOR _HID_DESCRIPTOR_LIST _HID_DESCRIPTOR DescriptorList 1 1 Array of one or more descriptors Table 503 _HID_DESCRIPTOR _HID_D...

Page 635: ...s bLUN uint8_tuint8_t _MSC_CBW bLUN bCBLength uint8_tuint8_t _MSC_CBW bCBLength CB uint8_tuint8_t _MSC_CBW CB 16 16 Table 506 _MSC_CSW class structure Member Description dSignature uint32_tuint32_t _M...

Page 636: ..._t uint8_t _USB_CORE_DESCS_T device_qualifier Pointer to USB device qualifier descriptor For full speed only implementation this pointer should be set to null 0 Table 510 _USB_DEVICE_QUALIFIER_DESCRIP...

Page 637: ...ptorType uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bDescriptorType INTERFACE Descriptor Type bInterfaceNumber uint8_tuint8_t _USB_INTERFACE_DESCRIPTOR bInterfaceNumber Number of this interface Zero bas...

Page 638: ...THER_SPEED_CONFIGURATION IConfiguration Index of string descriptor bmAttributes uint8_tuint8_t _USB_OTHER_SPEED_CONFIGURATION bmAttributes Same as Configuration descriptor bMaxPower uint8_tuint8_t _US...

Page 639: ...R bString UNICODE encoded string Table 516 _WB_T class structure Member Description L uint8_tuint8_t _WB_T L lower byte H uint8_tuint8_t _WB_T H upper byte Table 517 USBD_API class structure Member De...

Page 640: ...se memory location from where the stack can allocate data and buffers Remark The memory address set in this field should be accessible by USB DMA controller Also this value should be aligned on 2048 b...

Page 641: ...d disabled via the USB interrupt register USB_WakeUpCfg USB_PARAM_CB_TUSB_PARAM_CB_T USBD_API_INIT_PARAM USB_WakeUpCfg Event for remote walk up configuration when enabled This event fires when the USB...

Page 642: ...or operate properly USB_Feature_Event USB_CB_TUSB_CB_T USBD_API_INIT_PARAM USB_Feature_Event Event for USB feature changed This event fires when a the USB host send set clear feature request The stac...

Page 643: ...Notification uint16_t data Function to send CDC class notifications to host This function is called by application layer to send CDC class notifications to host See the USB CDC class specification doc...

Page 644: ...Class specific get request call back function This function is provided by the application software This function gets called when host sends CIC management element get requests Remark Applications i...

Page 645: ...request has data associated then this call back is called twice 1 First when setup request is received at this time application code could update pBuffer pointer to point to the intended destination T...

Page 646: ...error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions CDC_BulkOUT_Hdlr ErrorCode_t...

Page 647: ...vent is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions GetEncpsResp ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM GetEncpsResp USBD_HANDLE_T hCDC uint8_t buff...

Page 648: ...ess 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions GetCommFeature ErrorCode_t ErrorCode_t USBD_CDC_INIT_PARAM GetCommFeature U...

Page 649: ...ovided by the application software This function gets called when host sends a CLEAR_COMM_FEATURE request In the call back the application should Clears the settings for a particular communication fea...

Page 650: ...ype to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions Se...

Page 651: ...error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other error conditions CDC_InterruptEP_Hdlr ErrorCo...

Page 652: ...t in line 3 ERR_USBD_xxx For other error conditions Table 520 USBD_CDC_INIT_PARAM class structure Member Description Table 521 USBD_CORE_API class structure Member Description RegisterClassHandler Err...

Page 653: ...dlers SetupStage void void USBD_CORE_API SetupStage USBD_HANDLE_T hUsb Function to set EP0 state machine in setup state This function is called by USB stack and the application layer to set the EP0 st...

Page 654: ...er to set the EP0 state machine in status_in state This function will send zero length IN packet on EP0 to host indicating positive status Remark This interface is provided to users to invoke this fun...

Page 655: ...chine in stall state This function is called by USB stack and the application layer to generate STALL signalling on EP0 endpoint This function will also reset the EP0Data buffer Remark This interface...

Page 656: ...tion parameters Returns Returns the required memory size in bytes init ErrorCode_t ErrorCode_t USBD_DFU_API init USBD_HANDLE_T hUsb USBD_DFU_INIT_PARAM_T param uint32_t init_state Function to initiali...

Page 657: ..._num uint8_t src uint32_t length uint8_t bwPollTimeout DFU Write callback function This function is provided by the application software This function gets called when host sends a write command For a...

Page 658: ...an be invoked only by kernel drivers on Windows host By implementing this feature host doesn t have to issue reset instead the device has to do it automatically by disconnect and connect procedure Par...

Page 659: ...lization parameters Returns Returns the required memory size in bytes init ErrorCode_t ErrorCode_t USBD_HID_API init USBD_HANDLE_T hUsb USBD_HID_INIT_PARAM_T param Function to initialize HID function...

Page 660: ...n array of HID report descriptor data structure Remark This array should be of global scope HID_GetReport ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HID_GetReport USBD_HANDLE_T hHid USB_SETUP_PACKET...

Page 661: ...gth Optional callback function to handle HID_GetPhysDesc request The application software could provide this callback HID_GetPhysDesc handler to handle get physical descriptor requests sent by the hos...

Page 662: ...eturns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK On success 2 ERR_USBD_UNHANDLED Event is not handled hence pass the event to next in line 3 ERR_USBD_xxx For other...

Page 663: ...endpoint event handler Application which send reports to host on interrupt endpoint should provide an endpoint event handler through this data member This data member is ignored if the interface desc...

Page 664: ...o next in line 3 ERR_USBD_xxx For other error conditions HID_GetReportDesc ErrorCode_t ErrorCode_t USBD_HID_INIT_PARAM HID_GetReportDesc USBD_HANDLE_T hHid USB_SETUP_PACKET pSetup uint8_t pBuf uint16_...

Page 665: ...on software could override the default EP0 class handler with their own by providing the handler function address as this data member of the parameter structure Application which like the default hand...

Page 666: ...On successful initialization the function returns a handle to USB device stack which should be passed to the rest of the functions Parameters 1 phUsb Pointer to the USB device stack handle of type USB...

Page 667: ...device stack Returns Nothing Reset void void USBD_HW_API Reset USBD_HANDLE_T hUsb Function to Reset USB device stack and hardware controller Reset USB device stack and hardware controller Disables al...

Page 668: ...t USB address assigned by host in device controller hardware This function is called automatically when USB_REQUEST_SET_ADDRESS request is received by the stack from USB host This interface is provide...

Page 669: ...o are selectively modifying the USB device stack s standard handlers through callback interface exposed by the stack Parameters 1 hUsb Handle to the USB device stack 2 pEPD Endpoint descriptor structu...

Page 670: ...0x0 3 event Type of endpoint event See USBD_EVENT_T for more details 4 enable 1 enable event 0 disable event Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC...

Page 671: ...Parameters 1 hUsb Handle to the USB device stack 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number Returns Nothing SetTestMode ErrorCode_t ErrorCode_t USBD_H...

Page 672: ...T hUsb uint32_t EPNum uint8_t pData uint32_t len Function to queue read request on the specified endpoint This function is called by USB stack and the application layer to queue a read request on the...

Page 673: ...ck 2 EPNum Endpoint number as per USB specification ie An EP1_IN is represented by 0x81 number 3 pData Pointer to the data buffer from where data is to be copied 4 cnt Number of bytes to write Returns...

Page 674: ...e memory areas are not accessible by all bus masters Parameters 1 param Structure containing MSC function driver module initialization parameters Returns Returns the required memory size in bytes init...

Page 675: ...nse to the SCSI Inquiry command Remark The data pointed by the pointer should be of global scope BlockCount uint32_tuint32_t USBD_MSC_INIT_PARAM BlockCount Number of blocks present in the mass storage...

Page 676: ...rs implemented in stack are written with zero copy model Meaning the stack doesn t make an extra copy of buffer before writing reading data from USB hardware FIFO Hence the parameter is pointer to a p...

Page 677: ...containing the data sent by the host 3 length Number of bytes to verify Returns Returns ErrorCode_t type to indicate success or error condition Return values 1 LPC_OK If data in the buffer matches th...

Page 678: ...by providing the handler function address as this data member of the parameter structure Application which like the default handler should set this data member to zero before calling the USBD_MSC_API...

Page 679: ...50 26 3 Features 10 100 Mbit s DMA support IEEE 1588 time stamping block IEEE 1588 advanced time stamp support IEEE 1588 2008 v2 Power management remote wake up frame and magic packet detection Suppor...

Page 680: ...nd reception with Scatter Gather DMA off loads many operations from the CPU Additional features such as IEEE 1588 Time Stamping IEEE 1588 2002 and IEEE Advanced Time Stamp support IEEE 1588 2008 v2 en...

Page 681: ...Ethernet MIIM Clock RMII interface ENET_RXD 1 0 I Ethernet Receive Data ENET_TXD 1 0 O Ethernet Transmit Data ENET_RX_DV I Ethernet Receive Data Valid ENET_REF_CLK I Ethernet Reference Clock ENET_TX_...

Page 682: ...rol and status 0x0000 0000 Table 543 0x0030 0x0034 Reserved MAC_INTR RO 0x0038 Interrupt status register 0x0000 0000 Table 544 MAC_INTR_MASK R W 0x003C Interrupt mask register 0x0000 0000 Table 545 MA...

Page 683: ...DMA_CURHOST_TRANS_DES RO 0x1048 Current host transmit descriptor register 0x0000 0000 Table 571 DMA_CURHOST_REC_DES RO 0x104C Current host receive descriptor register 0x0000 0000 Table 572 DMA_CURHOS...

Page 684: ...imes for 1000 Mbps and 512 bit times for 10 100 Mbps the MAC waits before rescheduling a transmission attempt during retries after a collision This bit is applicable only to Half Duplex mode and is re...

Page 685: ...ps 0 15 PS Port select 1 MII 100 Mbp this is the only allowed value 1 RO 16 DCRS Disable carrier sense during transmission When set high this bit makes the MAC transmitter ignore the MII CRS signal du...

Page 686: ...E is set high of the frame being received and cuts off any bytes received after that 0 R W 31 24 Reserved 0x00 RO Table 532 MAC Configuration register MAC_CONFIG address 0x4001 0000 bit description co...

Page 687: ...l frames depends only on RFE of the Flow Control Register 00 MAC filters all control frames from reaching the application 01 MAC forwards all control frames except PAUSE control frames to application...

Page 688: ...ain when double synchronization is enabled The Hash Table High register contains the higher 32 bits of the Hash table 26 6 4 MAC Hash table low register The Hash Table Low register contains the lower...

Page 689: ...te operation using the MII Data register If this bit is not set this will be a Read operation placing the data in the MII Data register 0 R W 5 2 CR CSR clock range The CSR Clock Range selection deter...

Page 690: ...l block to generate a Pause Control frame The fields of the control frame are selected as specified in the 802 3x specification and the Pause Time value from this register is used in the Pause Time fi...

Page 691: ...nput signal for the backpressure function When the MAC is configured to Full Duplex mode the BPA is automatically disabled 0 R W 1 TFE Transmit Flow Control Enable In Full Duplex mode when this bit is...

Page 692: ...16 PT Pause time This field holds the value to be used in the Pause Time field in the transmit control frame If the Pause Time bits is configured to be double synchronized to the MII clock domain then...

Page 693: ...ill level below flow control de activate threshold 10 RxFIFO fill level above flow control activate threshold 11 RxFIFO Full 0 RO 15 10 Reserved RO 16 TXIDLESTAT When high it indicates that the MAC MI...

Page 694: ...description Bit Symbol Description Reset value Access 0 PD Power down This register field can be read by the application Read can be set to 1 by the application with a register write of 1 Write Set an...

Page 695: ...be a wake up frame 0 R W 30 10 Reserved 0x00 0000 RO 31 WFFRPR Wake up Frame Filter Register Pointer Reset This register field can be read by the application Read can be set to 1 by the application w...

Page 696: ...eeds the value specified in the Target Time High and Low registers There is an overflow in the seconds register This bit is cleared on reading the byte 0 of the Timestamp Status register Table 559 Oth...

Page 697: ...on 26 6 16 MAC IEEE1588 time stamp control register This register controls the operation of the System Time generator and the snooping of PTP packets for time stamping in the Receiver Table 546 MAC Ad...

Page 698: ...0 by the Ethernet core Self Clear When set the system time is updated added subtracted with the value specified in the Time Stamp High Update and Time Stamp Low Update registers This register bit shou...

Page 699: ...t is taken for all other messages except Announce Management and Signaling 0 R W 15 TSMSTRENA Enable Snapshot for Messages Relevant to Master When set the snapshot is taken for messages relevant to ma...

Page 700: ...pdated on a continuous basis there is some delay from the actual time due to clock domain transfer latencies 26 6 19 System time nanoseconds register This register contains 32 bits of the nano seconds...

Page 701: ...lue Table 552 System time nanoseconds register NANOSECONDS address 0x4001 070C bit description Bit Symbol Description Reset value Access 30 0 TSSS Time stamp sub seconds The value in this field has th...

Page 702: ...gisters Table 554 System time nanoseconds update register NANOSECONDSUPDATE address 0x4001 0714 bit description Bit Symbol Description Reset value Access 30 0 TSSS Time stamp sub seconds The value in...

Page 703: ...automatically cleared to 0 on a register read A register write of 0 has no effect on this field Table 557 Target time nanoseconds register TARGETNANOSECONDS address 0x4001 0720 bit description Bit Sym...

Page 704: ...ar this type of field and a register write of 0 to this bit has no effect on this field When this bit is set the MAC DMA Controller resets all MAC Subsystem internal registers and logic It is cleared...

Page 705: ...DMA requests in the following ratio This is valid only when the DA bit is reset 00 1 to 1 01 2 to 1 10 3 to 1 11 4 to 1 00 R W 16 FB Fixed burst This bit controls whether the AHB Master interface perf...

Page 706: ...will start all bursts of length more than 16 with INCR undefined burst whereas it will revert to fixed burst transfers INCRx and SINGLE for burst length of 16 and below 0 R W 27 TXPR When set this bit...

Page 707: ...host s physical memory space and must be Word aligned The DMA internally converts it to bus width aligned address by making the corresponding LSB to low Writing to this register is permitted only when...

Page 708: ...will be ignored and taken as all zero by the DMA internally Hence these LSB bits are Read Only 0 R W Table 566 DMA Status register DMA_STAT address 0x4001 1014 bit description Bit Symbol Description...

Page 709: ...eceived This bit is set only when the previous Receive Descriptor was owned by the DMA 0 R W 8 RPS Received process stopped This bit is asserted when the Receive Process enters the Stopped state 0 R W...

Page 710: ...bit 8 Receive process stopped DMA_STAT register bit 9 Receive watchdog timeout DMA_STAT register bit 10 Early transmit interrupt DMA_STAT register bit 13 Fatal bus error Only unmasked bits affect the...

Page 711: ...frame of Transmit data even before status for first frame is obtained 0 R W 4 3 RTC Receive threshold control These two bits control the threshold level of the MTL Receive FIFO Transfer request to DM...

Page 712: ...rol These three bits control the threshold level of the MTL Transmit FIFO Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold In addition full frames with...

Page 713: ...ister Transmission Stopped Interrupt is enabled When this bit is reset Transmission Stopped Interrupt is disabled 0 R W 2 TUE Transmit buffer unavailable enable When this bit is set with Normal Interr...

Page 714: ...rupt is enabled When this bit is reset Fatal Bus Error Enable Interrupt is disabled 0 R W 14 ERE Early receive interrupt enable When this bit is set with Normal Interrupt Summary Enable bit 16 in this...

Page 715: ...wo counters to track the number of missed frames during reception This register reports the current value of the counter The counter is used for diagnostic purposes Bits 15 0 indicate missed frames du...

Page 716: ...MA discards an incoming frame The counter is cleared when this register is read with 0 RO 16 OC Overflow bit for missed frame counter This register field can be read by the application Read can be set...

Page 717: ...s 7 0 RIWT RI watchdog timeout Indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set The watchdog timer gets triggered with the programmed value after the R...

Page 718: ...mode only when either a Magic Packet or a Remote Wake up frame is received and the corresponding detection is enabled 26 7 1 1 Remote wake up frame registers The register WKUPFMFILTER_REG address 0x0...

Page 719: ...ich filter i examines the frames This 8 bit pattern offset is the offset for the filter i first byte to be examined The minimum allowed is 12 which refers to the 13th byte of the frame The offset valu...

Page 720: ...o the node on the network Only Magic Packets that are addressed to the device or a broadcast address will be checked to determine whether they meet the wake up requirements Magic Packets that pass the...

Page 721: ...mode by appropriately configuring the PMT registers 5 Enable the MAC Receiver and enter Power Down mode 6 Gate the application and transmit clock inputs to the core and other relevant clocks in the s...

Page 722: ...s of varying inherent precision resolution and stability to synchronize The protocol supports system wide synchronization accuracy in the sub microsecond range with minimal network and local clock com...

Page 723: ...e captured for Ethernet ports at MII 2 The slave receives the Sync message and also captures the exact time t2 using its timing reference 3 The master sends a Follow_up message to the slave which cont...

Page 724: ...ule and updated using the input reference clock This time is the source for taking snapshots timestamps of Ethernet frames being transmitted or received at the MII The System Time counter can be initi...

Page 725: ...lower to 65 MHz for example the ratio is 65 50 or 1 3 and the value to set in the addend register is 232 1 30 or 0xC4EC4EC4 If the clock drifts higher to 67 MHz for example the addend register must be...

Page 726: ...ven by ClockDiffCountn MasterClockCountn SlaveClockCountn The frequency scaling factor for slave clock FreqScaleFactorn is given by FreqScaleFactorn MasterClockCountn ClockDiffCountn SlaveClockCountn...

Page 727: ...the DMA does not alter RDES6 or RDES7 26 7 3 5 Timestamp error margin According to the IEEE 1588 specifications a timestamp must be captured at the SFD of the transmitted and received frames at the M...

Page 728: ...ames Provides an option to take snapshot of only event messages Provides an option to take the snapshot based on the clock type ordinary boundary end to end and peer to peer Provides an option to sele...

Page 729: ...two ports Port 2 returns the Pdelay_Resp message as quickly as possible after the receipt of the Pdelay_Req message The Port 2 returns any one of the following The difference between the timestamps t...

Page 730: ...g PTP message types version 1 or version 2 You cannot take the snapshots for both PTP message types You can take the snapshot by setting the control bit TSVER2ENA and selecting the snapshot mode in Ta...

Page 731: ...king snapshot for the event messages related to Pdelay is added The transparent clock corrects only the SYNC and Follow up message As discussed earlier this can be achieved using the message status pr...

Page 732: ...or the tagged frames are offset by 4 This is based on Annex D of IEEE 1588 2008 standard and the message format defined in Table 578 sequenceId 2 30 controlField 1 1 32 logMessageInterva 1 33 Table 58...

Page 733: ...Resp 0x04 Management PTP Message Type Field IEEE version 2 42 nibble 0x0 0x1 0x2 0x3 0x8 0x9 0xB 0xC 0xD 0x0 SYNC 0x1 Delay_Req 0x2 Pdelay_Req 0x3 Pdelay_Resp 0x8 Follow_Up 0x9 Delay_Resp 0xA Pdelay_R...

Page 734: ...Follow_Up 0x9 Delay_Resp 0xA Pdelay_Resp_Follow_Up 0xB Announce 0xC Signaling 0xD Management PTP Version 75 nibble 0x1 or 0x2 0x1 Supports PTP version 1 0x2 Supports PTP version 2 Table 582 IPv6 UDP P...

Page 735: ...ds field is the fractional portion of the timestamp in units of nanoseconds For example 2 000000001 nanoseconds are represented as nanoSeconds 0x0000_0001 The nanoseconds field supports the following...

Page 736: ...ernet controller also supports PTP messages over VLAN frames The MAC provides the timestamp along with EOF An additional signal validates the presence of timestamp for the receive frame The MTL provid...

Page 737: ...transmission The base address of each list is written into DMA Registers Table 564 and Table 565 A descriptor list is forward linked either implicitly or explicitly The last descriptor may point back...

Page 738: ...A with the starting address of each list 4 Write to MAC Registers Table 533 Table 535 and Table 534 for desired filtering options 5 Write to MAC Register Table 532 to configure the operating mode and...

Page 739: ...configured burst length is detected in the Receive FIFO The DMA indicates the start address and the number of transfers required to the AHB Master Interface When the AHB Interface is configured for f...

Page 740: ...If a descriptor is marked as last then the buffer may not be full as indicated by the buffer size in RDES1 To compute the amount of valid data in this final buffer the driver must read the frame lengt...

Page 741: ...ffer address from the acquired descriptor 5 The DMA fetches the Transmit data from the Host memory and transfers the data to the MTL for transmission 6 If an Ethernet frame is stored over data buffers...

Page 742: ...atus descriptor of the first if the OSF bit is set in DMA Operation mode register bit 2 As the transmit process finishes transferring the first frame it Fig 72 TxDMA operation in default mode Start Tx...

Page 743: ...transmission status and time stamp Once the status is available the DMA writes the time stamp to TDES2 and TDES3 if such time stamp was captured as indicated by a status bit The DMA then writes the st...

Page 744: ...s word to prev frame s TDES0 Transfer data from buffer s AHB error Own bit set AHB error Frame xfer complete Time stamp present AHB error Write time stamp to TDES2 TDES3 for previous frame AHB error S...

Page 745: ...mpletion TDES1 31 was set Transmit Interrupt DMA Status register bit 0 is set the Next Descriptor is fetched and the process repeats The actual frame transmission begins after the MTL Transmit FIFO ha...

Page 746: ...d the DMA sets the Descriptor Error bit in the RDES0 unless flushing is disabled The DMA closes the current descriptor clears the Own bit and marks it as intermediate by clearing the Last Segment LS b...

Page 747: ...Re Fetch next descriptor AHB error No Own bit set Yes Yes Stop RxDMA Start RxDMA Start AHB error No RxDMA suspended Yes Frame data available Wait for frame data Write data to buffer s Yes Yes Fetch n...

Page 748: ...in Store and Forward mode If the frame fails the address filtering it is dropped in the MAC block itself unless Receive All bit 31 is set in the MAC Frame Filter register Table 533 Frames that are sho...

Page 749: ...A Interrupt Enable Register Table 568 Interrupts are not queued and if the interrupt event occurs before the driver has responded to it no additional interrupts are generated For example the Receive I...

Page 750: ...RDS of memory for every descriptor When Timestamping or Receive IPC FullOffload engine are not enabled the extended descriptors are not required and the SW can use alternate descriptors with the defau...

Page 751: ...Advanced timestamp feature support is enabled TDES0 has additional control bits 6 3 for channel 1 and channel 2 For channel 0 the bits 6 3 are ignored The bits 6 3 are described in Table 584 Fig 75 T...

Page 752: ...ocess enters the Suspended state and sets both Transmit Underflow Register 5 5 and Transmit Interrupt Register 5 0 2 ED Excessive Deferral When set this bit indicates that the transmission has ended b...

Page 753: ...issues an error status in case of a mismatch 13 FF Frame Flushed When set this bit indicates that the DMA MTL flushed the frame due to a software Flush command given by the CPU 14 JT Jabber Timeout Wh...

Page 754: ...valid only when the first segment TDES0 28 is set 28 FS First Segment When set this bit indicates that the buffer contains the first segment of a frame 29 LS Last Segment When set this bit indicates...

Page 755: ...TDES3 Bit Symbol Description 31 0 B2ADD Buffer 2 Address Pointer Next Descriptor Address Indicates the physical address of Buffer 2 when a descriptor ring structure is used If the Second Address Chain...

Page 756: ...ble 590 The contents of RDES1 through RDES3 are identified in Table 591 to Table 593 Fig 77 Receive descriptor fields alternate configuration O W N Status 30 0 Buffer 1 Address 31 0 Buffer 2 Address 3...

Page 757: ...be of less no extension or error rxd 0f during extension 4 RWT Receive Watchdog Timeout When set this bit indicates that the Receive Watchdog Timer has expired while receiving the current frame and t...

Page 758: ...Collision RDES0 7 Giant Frame RDES4 4 3 IP Header Payload Error RDES0 11 Overflow Error RDES0 14 Descriptor Error This field is valid only when the Last Descriptor RDES0 8 is set 29 16 FL Frame Lengt...

Page 759: ...4 the resulting behavior is undefined This field is not valid if RDES1 14 is set See Section 26 7 5 1 3 for further details on calculating buffer sizes Table 592 Receive descriptor fields 2 RDES2 Bit...

Page 760: ...ed 0000 No PTP message received 0001 SYNC all clock types 0010 Follow_Up all clock types 0011 Delay_Req all clock types 0100 Delay_Resp all clock types 0101 Pdelay_Req in peer to peer transparent cloc...

Page 761: ...ter 26 LPC43xx Ethernet Table 596 Receive descriptor fields 7 RDES7 Bit Symbol Description 31 0 RTSH Receive Frame Timestamp High This field is updated by DMA with the most significant 32 bits of the...

Page 762: ...isplays Programmable display resolution including but not limited to 320x200 320x240 640x200 640x240 640x480 800x600 and 1024x768 Hardware cursor support for single panel displays 15 gray level monoch...

Page 763: ...STN displays either a value obtained from the addressed palette location or the true value is passed to the gray scaling generators The hardware coded gray scale algorithm logic sequences the activit...

Page 764: ...dth Number of lines per panel Number of pixel clocks per line Hardware cursor control Signal polarity active HIGH or LOW AC panel bias Panel clock frequency Bits per pixel Fig 78 LCD controller block...

Page 765: ...ves the requirement for this management by providing a completely separate image buffer for the cursor and superimposing the cursor image on the LCD output stream at the current cursor X Y coordinate...

Page 766: ...s selected from 3375 2 bpp palettized 4 colors selected from 3375 4 bpp palettized 16 colors selected from 3375 8 bpp palettized 256 colors selected from 3375 16 bpp direct 4 4 4 RGB with 4 bpp not be...

Page 767: ...nel data LCDLP Output Line synchronization pulse STN Horizontal synchronization pulse TFT LCDVD 23 0 Output LCD panel data Bits used depend on the panel configuration GP_CLKIN Input General purpose CG...

Page 768: ...ys Pin name 12 bit 4 4 4 mode 18 pins 16 bit 5 6 5 mode 22 pins 16 bit 1 5 5 5 mode 24 pins 24 bit 30 pins LCDPWR Y Y Y Y LCDDCLK Y Y Y Y LCDENAB LCDM Y Y Y Y LCDFP Y Y Y Y LCDLE Y Y Y Y LCDLP Y Y Y Y...

Page 769: ...Interrupt Clear register 0x0 Table 613 UPCURR RO 0x02C Upper Panel Current Address Value register 0x0 Table 614 LPCURR RO 0x030 Lower Panel Current Address Value register 0x0 Table 615 0x034 to 0x1FC...

Page 770: ...bit value that represents between 16 and 1024 pixels per line PPL counts the number of pixel clocks that occur before the HFP is applied Program the value required divided by 16 minus 1 Actual pixels...

Page 771: ...on pulse Program the register with the number of lines required minus one The number of horizontal synchronization lines must be small for example program to zero for passive STN LCDs The higher the v...

Page 772: ...CDDCLK LCDCLK 6 Single panel monochrome 4 bit interface mode PCD 2 LCDDCLK LCDCLK 4 Dual panel monochrome 4 bit interface mode and single panel monochrome 8 bit interface mode PCD 6 LCDDCLK LCDCLK 8 D...

Page 773: ...able that indicates to the LCD panel when valid display data is available In active display mode data is driven onto the LCD data lines at the programmed edge of LCDDCLK when LCDENAB is in its active...

Page 774: ...ller The base address must be doubleword aligned Optionally the value may be changed mid frame to create double buffered video displays These registers are copied to the corresponding current register...

Page 775: ...n Reset value 0 LCDEN LCD enable control bit 0 LCD disabled Signals LCDLP LCDDCLK LCDFP LCDENAB and LCDLE are low 1 LCD enabled Signals LCDLP LCDDCLK LCDFP LCDENAB and LCDLE are high See LCD power up...

Page 776: ...R LCD power enable 0 power not gated through to LCD panel and LCDV 23 0 signals disabled held LOW 1 power gated through to LCD panel and LCDV 23 0 signals enabled active See LCD power up and power dow...

Page 777: ...he LCD base address registers have been updated from the next address registers 0x0 3 VCOMPIM Vertical compare interrupt enable 0 The vertical compare time interrupt is disabled 1 Interrupt will be ge...

Page 778: ...d user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 611 Raw Interrupt Status register INTRAW address 0x4000 8020 bit description Bit Symbol D...

Page 779: ...ol Description Reset value 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 1 FUFIC FIFO underflow interrupt clear Writing a 1 to this...

Page 780: ...Cursor Configuration register description the cursor image RAM contains either four 32x32 cursor images or a single 64x64 cursor image The two colors defined for the cursor are mapped onto values fro...

Page 781: ...meSync is 0 the cursor image index is changed immediately even if the cursor is currently being scanned 27 6 17 Cursor Configuration register The CRSR_CFG register provides overall configuration infor...

Page 782: ...ayed according to the abilities of the LCD panel in the same way as the frame buffers palette output is displayed In monochrome STN mode only the upper 4 bits of the Red field are used In STN color mo...

Page 783: ...CFG register is 1 the displayed cursor image is only changed during the vertical frame blanking period providing that the cursor position has been updated since the Clip register was programmed When p...

Page 784: ...13 8 CRSRCLIPY Cursor clip position for Y direction Distance from the top of the cursor image to the first displayed pixel in the cursor When 0 the first displayed pixel is from the top line of the cu...

Page 785: ...memory 27 7 1 1 AMBA AHB slave interface The AHB slave interface connects the LCD controller to the AHB bus and provides CPU accesses to the registers and palette RAM Table 626 Cursor Raw Interrupt St...

Page 786: ...t inserts busy cycles if the FIFOs have not completed their synchronization and updating sequence Fills up the DMA FIFOs in dual panel mode in an alternating fashion from a single DMA request Asserts...

Page 787: ...r each of the three supported data formats the required data for each panel display pixel must be extracted from the data word Table 628 FIFO bits for Little endian Byte Little endian Pixel order FIFO...

Page 788: ...ble 629 FIFO bits for Big endian Byte Big endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 31 p0 p0 p0 p0 p0 30 p1 29 p2 p1 28 p3 27 p4 p2 p1 26 p5 25 p6 p3 24 p7 23 p8 p4 p2 p1 p0 22...

Page 789: ...in each DMA FIFO word in RGB mode Table 630 FIFO bits for Little endian Byte Big endian Pixel order FIFO bit 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp 31 p24 p12 p6 p3 p1 30 p25 29 p26 p13 28 p27 27 p28...

Page 790: ...e 1 p1 Blue 0 p1 Blue 3 26 p1 Blue 0 p1 Green 5 p1 Blue 2 25 p1 Green 4 p1 Green 4 p1 Blue 1 24 p1 Green 3 p1 Green 3 p1 Blue 0 23 p0 Blue 7 p1 Green 2 p1 Green 2 p1 Green 3 22 p0 Blue 6 p1 Green 1 p1...

Page 791: ...of the pixel serializer is used as the TFT panel data The red and blue pixel data can be swapped to support BGR data format using a control register bit bit 8 BGR See the CTRL register description fo...

Page 792: ...terface This also provides a read write port to the cursor image RAM 27 7 5 1 Cursor operation The hardware cursor is contained in a dual port RAM It is programmed by software through the AHB slave in...

Page 793: ...s are supported as shown in Table 635 27 7 5 3 Cursor movement The following descriptions assume that both the screen and cursor origins are at the top left of the visible screen the first visible pix...

Page 794: ...mage The cursor image is clipped automatically at the screen limits when it extends beyond the screen image to the right or bottom see X1 Y1 in Figure 80 The checked pattern shows the visible portion...

Page 795: ...r description in this chapter The displayed cursor coordinate system is expressed in terms of X Y 64 x 64 is an extension of the 32 x 32 format shown in Figure 81 32 by 32 pixel format Four cursors ar...

Page 796: ...31 13 12 5 0 21 0 5 y 21 y 5 31 21 31 11 10 6 0 22 0 6 y 22 y 6 31 22 31 9 8 7 0 23 0 7 y 23 y 7 31 23 31 7 6 0 0 16 0 0 y 16 y 0 31 16 31 5 4 1 0 17 0 1 y 17 y 1 31 17 31 3 2 2 0 18 0 2 y 18 y 2 31...

Page 797: ...wer panel formatters Formatters are used in STN mode to convert the gray scaler output to a parallel format as required by the display For monochrome displays this is either 4 or 8 bits wide and for c...

Page 798: ...the LCD panel being used The CLKSEL bit in the POL register determines whether the base clock used is CCLK or the LCDCLKIN pin 27 7 9 Timing controller The primary function of the timing controller b...

Page 799: ...cleared by writing a 1 to the BERIC bit in the INTCLR register This action releases the master interface from its ERROR state to the start of FRAME state and enables fresh frame of data display to be...

Page 800: ...abilized the contrast voltage not controlled or supplied by the LCD controller is applied to the LCD panel 4 If required a software or hardware timer can be used to provide the minimum display specifi...

Page 801: ...Rev 1 3 6 July 2012 801 of 1269 NXP Semiconductors UM10503 Chapter 27 LPC43xx LCD Fig 82 Power up and power down sequences LCDLP LCDCP LCDFP LCDAC LCDLE LCD Power Contrast Voltage LCDPWR LCD 23 0 Mini...

Page 802: ...nd scaled by the LCD controller and used to produce LCDCLK 3 The duration of the LCDLP signal is controlled by the HSW field in the TIMH register 4 The Polarity of the LCDLP signal is determined by th...

Page 803: ...nes for one frame see horizontal timing for STN displays panel data clock active 1 The active data lines will vary with the type of TFT panel 2 The LCD panel clock is selected and scaled by the LCD co...

Page 804: ...porch defined in line clocks front porch defined in line clocks pixel data and horizontal control signals for one frame one frame all horizontal lines for one frame see horizontal timing for TFT disp...

Page 805: ..._7 LCDPWR P7_7 LCDPWR GP_CLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN PF_4 LCDCLKIN Table 641 LCD panel connections for STN single panel mode External pin 4 bit mono STN single panel 8 bit mono STN single panel...

Page 806: ...unction LPC43xx pin used LCD function Table 643 LCD panel connections for TFT panels External pin TFT 12 bit 4 4 4 mode TFT 16 bit 5 6 5 mode TFT 16 bit 1 5 5 5 mode TFT 24 bit LPC43xx pin used LCD fu...

Page 807: ...P4_6 LCDENAB LCDM P4_6 LCDENAB LCDM P4_6 LCDENAB L CDM LCDFP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP P4_5 LCDFP LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK P4_7 LCDDCLK LCDLE P7_0 LCDLE P7_0 LCDLE P7_0 LC...

Page 808: ...d with various timer match outputs if bit CTOUTCTRL in CREG6 is zero see Table 50 this is the default Set the CTOUTCTRL bit to one to use the SCT outputs without interference from the timers 28 3 Feat...

Page 809: ...or a unified 32 bit counter In the two counter case in addition to the counter value the following operational elements are independent for each half State variable Limit halt stop and start condition...

Page 810: ...to the CTOUT_n pins and are ORed with timer match outputs when the CTOUCTRL bit is set to 0 in CREG6 see Table 50 this is the default Some SCT outputs are connected to multiple destinations at once f...

Page 811: ...SCT output 1 ORed with Timer3 match output 3 CTOUT_1 0 SCT output 1 CTOUT_1 1 SCT output 2 ORed with Timer0 match output 2 CTOUT_2 Event router input 13 0 SCT output 2 CTOUT_2 Event router input 13 1...

Page 812: ...ing to the CONFIG register before any other registers are accessed SCT output 8 ORed with Timer2 match output 0 CTOUT_8 ADC start1 input ADC CR register bit START 0x3 0 SCT output 8 CTOUT_8 ADC start1...

Page 813: ...r 0x0000 0000 Table 651 STOP_L R W 0x010 SCT stop condition register low counter 16 bit 0x0000 0000 Table 651 STOP_H R W 0x012 SCT stop condition register high counter 16 bit 0x0000 0000 Table 651 STA...

Page 814: ...0 Table 667 MATCH0 to MATCH15 R W 0x180 to 0x1BC MATCH alias register see Section 28 7 9 SCT match value register of match channels 0 to 15 REGMOD0 to REGMODE15 0 0x0000 0000 Table 665 MATCH0_L to MAT...

Page 815: ...15 REGMOD0 1 to REGMODE15 1 0x0000 0000 Table 669 CAPCTRL0_L to CAPCTRL15_L 0x280 to 0x2BC CAPCTRL alias registers see Section 28 7 9 SCT capture control register 0 to 15 low counter 16 bit REGMOD0_L...

Page 816: ...0000 Table 673 OUTPUTSET1 R W 0x508 SCT output 1 set register 0x0000 0000 Table 672 OUTPUTCL1 R W 0x50C SCT output 1 clear register 0x0000 0000 Table 673 OUTPUTSET2 R W 0x510 SCT output 2 set registe...

Page 817: ...d Name Access Address offset Description Reset value Reference Table 647 SCT configuration register CONFIG address 0x4000 0000 bit description Bit Symbol Value Description Reset value 0 UNIFY SCT oper...

Page 818: ...dges on input 4 0x9 Falling edges on input 4 0xA Rising edges on input 5 0xB Falling edges on input 5 0xC Rising edges on input 6 0xD Falling edges on input 6 0xE Rising edges on input 7 0xF Falling e...

Page 819: ...ounter counts up to its limit then counts down to 0 12 5 PRE_L Specifies the factor by which the SCT clock is prescaled to produce the L or unified counter clock The counter clock is clocked at the ra...

Page 820: ...LT_H address 0x4000 400E Both the L and H registers can be read or written individually or in a single 32 bit read or write operation Remark Any event halting the counter disables its operation until...

Page 821: ...is case the L and H registers count independently under the control of the other registers Attempting to write a counter while it is running does not affect the counter but produces a bus error Softwa...

Page 822: ...rrupts and DMA requests modify the state variable The value of a state variable is completely under the control of the application If an application does not use states the value of the state variable...

Page 823: ...ister which serves as a Reload register when the register is used as a Match register Section 28 6 21 or as a Capture Control register when the register is used as a capture register Section 28 6 22 R...

Page 824: ...5 0 registers operate as match registers 1 registers operate as capture registers 0 31 16 REGMOD_H Each bit controls one pair of match capture registers register 0 bit 16 register 1 bit 17 register 15...

Page 825: ...when counter L or the unified counter is counting down 0x2 Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 15 14 SETCLR7 Set clear operation on output 7 Value 0x3 is...

Page 826: ...s counting down 0x2 Set and clear are reversed when counter H is counting down Do not use if UNIFY 1 29 28 SETCLR14 Set clear operation on output 14 Value 0x3 is reserved Do not program this value 0 0...

Page 827: ...lear on output 5 0 0x0 No change 0x1 Set output or clear based on the SETCLR5 field 0x2 Clear output or set based on the SETCLR5 field 0x3 Toggle output 13 12 O6RES Effect of simultaneous set and clea...

Page 828: ...eld 0x2 Clear output or set based on the SETCLR11 field 0x3 Toggle output 25 24 O12RES Effect of simultaneous set and clear on output 12 0 0x0 No change 0x1 Set output or clear based on the SETCLR12 f...

Page 829: ...h_L Unified registers from the Reload_L Unified registers 31 DRQ0 This read only bit indicates the state of DMA Request 0 Table 661 SCT DMA 1 request register DMAREQ1 address 0x4000 0060 bit descripti...

Page 830: ...running does not affect the Match register and results in a bus error Match events occur in the SCT clock in which the counter is or would be incremented to the next value When a Match event limits it...

Page 831: ...d or write the lower 16 bits of the 32 bit value to be compared to the unified counter 0 31 16 MATCHn_H When UNIFY 0 read or write the 16 bit value to be compared to the H counter When UNIFY 1 read or...

Page 832: ...se states write 0x01 to this register to enable an event Since the state always remains at its reset value of 0 writing 0x01 effectively permanently state enables this event 28 6 24 SCT event control...

Page 833: ...escription Bit Symbol Value Description Reset value 3 0 MATCHSEL Selects the Match register associated with this event if any A match can occur only when the counter selected by the HEVENT bit is runn...

Page 834: ...carry out is ignored 1 STATEV value is loaded into STATE 19 15 STATEV This value is loaded into or added to the state selected by HEVENT depending on STATELD when this event is the highest numbered ev...

Page 835: ...1 Match logic 28 7 2 Capture logic 28 7 3 Event selection State variables allow control of the SCT across more than one cycle of the counter Counter matches input output edges and state values are com...

Page 836: ...errupt generation The SCT generates one interrupt to the NVIC Fig 91 Event selection select event i select MATCHSELi inputs IOSELi select STATEMASKi COMBMODEi IOCONDi outputs OUTSELi HEVENTi H STATE L...

Page 837: ...r is enabled in that clock 28 7 7 Match vs I O events Counter operation is complicated by the prescaler and by clock mode 01 in which the SCT clock is the bus clock However the prescaler and counter a...

Page 838: ...re is used there is a TransferSize value in each Linked List entry The GPDMA asserts the DMACCLR signal when that number of transfers has been completed which makes the SCT clear the request 28 7 9 Al...

Page 839: ...User manual Rev 1 3 6 July 2012 839 of 1269 NXP Semiconductors UM10503 Chapter 28 LPC43xx State Configurable Timer SCT MATCHREL1_L CAPCTRL1_L 0x204 0x282 MATCHREL1_H CAPCTRL1_H 0x206 0x2C2 Table 675...

Page 840: ...of the counter events can change the state multiple times and thus create a large variety of event controlled transitions on the SCT outputs and or interrupts Once configured the SCT can run continuou...

Page 841: ...or clear this output More than one event can change the output and each event can change multiple outputs 3 Define how each event affects the counter Set the corresponding event bit in the LIMIT regis...

Page 842: ...e counter contents when one or more events occur If the counter is in bidirectional mode the effect of set and clear of an output can be made to depend on whether the counter is counting up or down by...

Page 843: ...dard counter timer with external capture inputs and match outputs without using the state logic To operate the SCT without states configure the SCT as follows Write zero to the STATE register zero is...

Page 844: ...figure one match register for each match event by setting REGMODE_L bits 0 1 2 4 5 to 0 This is the default Define match values MATCH0 1 2 4 5 Set a match value MATCH0 1 2 4 5_L in each register Defin...

Page 845: ...bits 1 for events 1 and 5 for event 5 to one to clear the output when events 1 and 5 occur Define which event resets the counter LIMIT Set LIMMASK_L bit 2 to 1 for event 2 to limit the counter Set al...

Page 846: ...apture inputs and match outputs are configured through the GIMA see Section 16 3 All timer capture inputs are also connected to dedicated external pins see Section 16 3 and Section 15 3 11 29 3 Featur...

Page 847: ...lue when an input signal transitions optionally generating an interrupt Table 678 gives a brief summary of each of the Timer Counter related functions 29 4 1 Architecture The block diagram for TIMER C...

Page 848: ...block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 3 CAPTURE REGISTER 2 CAPTURE REGISTER 1 CAPTURE REGISTER 0 MATCH REGISTER 3 MATCH REG...

Page 849: ...Tn_MATm pin functions In addition the match outputs ORed with the SCT outputs can be monitored on the CTOUT pins provided that the CTOUTCTRL bit is set to 0 default in the CREG6 register see Table 50...

Page 850: ...signal Default see GIMA Table 148 CTOUTCTRL bit see Table 50 Timer1 inputs CAP0 CTIN_0 yes SGPIO12 no T1_CAP0 no CAP1 CTIN_3 yes T1_CAP1 no USART0 TX active no CAP2 CTIN_4 yes T1_CAP2 no CAP3 USART0...

Page 851: ...AP1 CTIN_1 yes T2_CAP1 no USART2 TX active no CAP2 I2S1_RX_MWS no CTIN_5 yes CAP3 T2_CAP2 no USART2 RX active no I2S1_TX_MWS no SCT output 7 OR T1 match channel 3 yes 0 SCT output 7 yes 1 T1 match cha...

Page 852: ...CAP2 CTIN_7 yes T3_CAP2 no USART3 RX active no SOF0 no CAP3 T3_CAP3 no SCT output 11 OR T2 match channel 3 yes 0 SCT output 11 yes 1 T2 match channel 3 no SOF1 no Timer3 outputs MAT0 T3_MAT0 MAT1 T3_...

Page 853: ...ached the TC is incremented and the PC is cleared The PC is observable and controllable through the bus interface 0 Table 688 MCR R W 0x014 Match Control Register The MCR is used to control if an inte...

Page 854: ...event does not cause an interrupt but a match register can be used to detect an overflow if needed Table 684 Timer interrupt registers IR addresses 0x4008 4000 TIMER0 0x4008 5000 TIMER1 0x400C 3000 TI...

Page 855: ...used to control what operations are performed when one of the Match Registers matches the Timer Counter The function of each of the bits is shown in Table 689 Table 686 Timer counter registers TC add...

Page 856: ...ted when MR2 matches the value in the TC 0 Interrupt is disabled 7 MR2R Reset on MR2 0 1 TC will be reset if MR2 matches it 0 Feature disabled 8 MR2S Stop on MR2 0 1 TC and PC will be stopped and TCR...

Page 857: ...programmed as 000 but capture and or interrupt can be selected for the other 3 CAP inputs Table 690 Timer match registers MR 0 3 addresses 0x4008 4018 MR0 to 0x4008 4024 M3 TIMER0 0x4008 5018 MR0 to 0...

Page 858: ...TC 0 This feature is disabled 8 CAP2I Interrupt on CAPn 2 event 0 1 A CR2 load due to a CAPn 2 event will generate an interrupt 0 This feature is disabled 9 CAP3RE Capture on CAPn 3 rising edge 0 1 A...

Page 859: ...othing depending on bits 7 6 of this register This bit can be driven onto a MATn 1 pin in a positive logic manner 0 low 1 high 0 2 EM2 External Match 2 When a match occurs between the TC and MR2 this...

Page 860: ...e corresponding External Match bit output to 0 MATn m pin is LOW if pinned out 0x2 Set the corresponding External Match bit output to 1 MATn m pin is HIGH if pinned out 0x3 Toggle the corresponding Ex...

Page 861: ...CTCR addresses 0x4008 4070 TIMER0 0x4008 5070 TIMER1 0x400C 3070 TIMER2 0x400C 4070 TIMER3 bit description Bit Symbol Value Description Reset value 1 0 CTMODE Counter Timer Mode This field selects whi...

Page 862: ...ct the GPDMA must be configured and the relevant timer DMA request selected as a DMA source via the CREG block see Table 46 When a timer is initially set up to generate a DMA request the request may a...

Page 863: ...ounter TC a 32 bit Limit register LIM a 32 bit Match register MAT a 10 bit dead time register DT and an associated 10 bit dead time counter a 32 bit capture register CAP two modulated outputs MCOA and...

Page 864: ...up again Each channel also includes a Match register that holds a smaller value than the Limit register In edge aligned mode the channel s outputs are switched whenever the TC matches either the Match...

Page 865: ...election TC0 Event selection TC1 Event selection TC2 Event selection MCCNTCON MCCAPCON MAT0 oper MAT0 write LIM0 oper LIM0 write CAP0 channel output control dead time counter DT0 A0 B0 MCCON RT0 cntl...

Page 866: ...0x000 PWM Control read address 0 Table 699 CON_SET WO 0x004 PWM Control set address Table 700 CON_CLR WO 0x008 PWM Control clear address Table 701 CAPCON RO 0x00C Capture Control read address 0 Table...

Page 867: ...er overview Motor Control Pulse Width Modulator MCPWM base address 0x400A 0000 Name Access Address offset Description Reset value Reference Table 699 MCPWM Control read address CON 0x400A 0000 bit des...

Page 868: ...MCOA2 and MCOB2 pins 0 0 Passive state is LOW active state is HIGH 1 Passive state is HIGH active state is LOW 19 DTE2 Controls the dead time feature for channel 1 0 0 Dead time disabled 1 Dead time...

Page 869: ...bit in the CON register 8 RUN1_SET Writing a one sets the corresponding bit in the CON register 9 CENTER1_SET Writing a one sets the corresponding bit in the CON register 10 POLA1_SET Writing a one s...

Page 870: ...ting a one clears the corresponding bit in the CON register 20 DISUP2_CLR Writing a one clears the corresponding bit in the CON register 28 2 1 Writing a one clears the corresponding bit in the CON re...

Page 871: ...s reset by a channel 2 capture event 0 31 21 Reserved Table 702 MCPWM Capture Control read address CAPCON 0x400A 000C bit description Bit Symbol Description Reset value Table 703 MCPWM Capture Control...

Page 872: ...ts the corresponding bits in the CAPCON register 31 21 Reserved Table 703 MCPWM Capture Control set address CAPCON_SET 0x400A 0010 bit description Bit Symbol Description Reset value Table 704 MCPWM Ca...

Page 873: ...nting up again 10 CAP1MCI2_RE_CLR Writing a one clears the corresponding bits in the CAPCON register 11 CAP1MCI2_FE_CLR Writing a one clears the corresponding bits in the CAPCON register 12 CAP2MCI0_R...

Page 874: ...until software stops the channel Reading an LIM address always returns the operating value Remark In timer mode the period of a channel s modulated MCO outputs is determined by its Limit register and...

Page 875: ...MCO outputs at the state B active A passive write its Match register with a higher value than you write to its Limit register The match never occurs To lock a channel s MCO outputs at the opposite sta...

Page 876: ...the underlying registers can be cleared by writing to the CAP_CLR address 30 7 9 MCPWM Interrupt registers The Motor Control PWM module includes the following interrupt sources Table 709 MCPWM Communi...

Page 877: ...for channels 0 1 2 ABORT Fast abort interrupt Table 712 MCPWM Interrupt Enable read address INTEN 0x400A 0050 bit description Bit Symbol Value Description Reset value 0 ILIM0 Limit interrupt for chan...

Page 878: ...rupt enable set register INTEN_SET address 0x400A 0054 bit description Bit Symbol Description Reset value 0 ILIM0_SET Writing a one sets the corresponding bit in INTEN thus enabling the interrupt 1 IM...

Page 879: ...clears the corresponding bit in INTEN thus disabling the interrupt 2 ICAP0_CLR Writing a one clears the corresponding bit in INTEN thus disabling the interrupt 3 Reserved 4 ILIM1_CLR Writing a one cle...

Page 880: ...ct counter 1 1 If MODE1 is 1 counter 1 advances on a rising edge on MCI0 7 TC1MCI0_FE Counter 1 falling edge mode channel 0 0 0 A falling edge on MCI0 does not affect counter 1 1 If MODE1 is 1 counter...

Page 881: ...s 1 counter 2 advances on a falling edge on MCI2 28 18 Reserved 29 CNTR0 Channel 0 counter timer mode 0 0 Channel 0 is in timer mode 1 Channel 0 is in counter mode 30 CNTR1 Channel 1 counter timer mod...

Page 882: ...C2MCI1_RE_SET Writing a one sets the corresponding bit in the CNTCON register 15 TC2MCI1_FE_SET Writing a one sets the corresponding bit in the CNTCON register 16 TC2MCI2_RE_SET Writing a one sets the...

Page 883: ...ponding bit in the CNTCON register 8 TC1MCI1_RE_CLR Writing a one clears the corresponding bit in the CNTCON register 9 TC1MCI1_FE_CLR Writing a one clears the corresponding bit in the CNTCON register...

Page 884: ...e Interrupt Controller 3 Reserved 4 ILIM1_F Limit interrupt flag for channel 1 0 0 This interrupt source is not contributing to the MCPWM interrupt request 1 If the corresponding bit in INTEN is 1 the...

Page 885: ...description Bit Symbol Description Reset value 0 ILIM0_F_SET Writing a one sets the corresponding bit in the INTF register thus possibly simulating hardware interrupt 1 IMAT0_F_SET Writing a one sets...

Page 886: ...ars the corresponding bit in INTEN thus disabling the interrupt 3 Reserved 4 ILIM1_F_CLR Writing a one clears the corresponding bit in INTEN thus disabling the interrupt 5 IMAT1_F_CLR Writing a one cl...

Page 887: ...ulated MCO outputs is determined by its Limit register and the pulse width at the start of the period is determined by its Match register If it suits your way of thinking consider the Limit register t...

Page 888: ...s A or B output changes from active to passive The transition of the other output from passive to active is delayed until the dead time counter reaches 0 During the dead time the MCOA and MCOB output...

Page 889: ...immediately Software can write to a TC register only when its channel is stopped 30 8 3 Fast Abort ABORT The MCPWM has an external input MCABORT When this input goes low all six MCO outputs assume the...

Page 890: ...a bit in the current commutation pattern register CP If a bit in the CP register is 0 its output pin has the logic level for the passive state of output MCOA0 The polarity of the off state is determi...

Page 891: ...ach channel controls its MCO output by comparing its MAT value to TC0 Figure 104 shows sample waveforms for the six MCO outputs in three phase AC mode The POLA bits are set to 0 for all three channels...

Page 892: ...hannel captures the value of its TC into its Capture register because a selected edge occurs on any of MCI0 2 When all three channels outputs are forced to A passive state because the MCABORT pin goes...

Page 893: ...for 2X or 4X position counting Velocity capture using built in timer Velocity compare function with less than interrupt Uses 32 bit registers for position and velocity Three position compare register...

Page 894: ...coder converts angular displacement into two pulse signals By monitoring both the number of pulses and the relative phase of the two signals you can track the position direction of rotation and veloci...

Page 895: ...block diagram Digital Filter dir clk _ pulse Inx gating Windowing Inx_ pulse i dx Pha Phb Quad Decoder Velocity Counter Velocity Capture Velocity Compare Velocity Reload Velocity Timer tim _int rst rs...

Page 896: ...29 CMPOS0 R W 0x014 position compare register 0 0xFFFF FFFF Table 730 CMPOS1 R W 0x018 position compare register 1 0xFFFF FFFF Table 731 CMPOS2 R W 0x01C position compare register 2 0xFFFF FFFF Table...

Page 897: ...Chapter 31 LPC43xx Quadrature Encoder Interface QEI INTSTAT RO 0xFE0 Interrupt status register 0 Table 748 IE RO 0xFE4 Interrupt enable register 0 Table 749 CLR WO 0xFE8 Interrupt status clear registe...

Page 898: ...Symbol Description Reset value 0 RESP Reset position counter When set 1 resets the position counter to all zeros Autoclears when the position counter is cleared 0 1 RESPI Reset position counter on in...

Page 899: ...ODE Capture Mode When 0 only PhA edges are counted 2X When 1 BOTH PhA and PhB edges are counted 4X increasing resolution but decreasing range 0 3 INVINX Invert Index When set inverts the sense of the...

Page 900: ...ns a position compare value This value is compared against the current value of the position register Interrupts can be enabled to interrupt when the compare value is less than equal to or greater tha...

Page 901: ...P the timer is reloaded with the value stored in the velocity reload register LOAD and the velocity interrupt TIM_Int is asserted 31 6 2 10 QEI Velocity register This register contains the running cou...

Page 902: ...zero bypasses the filter 31 6 2 14 QEI Digital filter on phase B input register This register contains the sampling count for the digital filter A sampling count of zero bypasses the filter 31 6 2 15...

Page 903: ...be enabled to interrupt when the compare value is less than equal to or greater than the current value of the index count register 31 6 2 18 QEI Index Compare register 2 This register contains an ind...

Page 904: ...sition 0 9 REV0_INT Indicates that the index 0 compare value is equal to the current index count 0 10 POS0REV_INT Combined position 0 and revolution count interrupt Set when both the POS0_INT bit is s...

Page 905: ...0 Table 747 QEI Interrupt Enable Set register IES address 0x400C 6FDC bit description Bit Symbol Description Reset value Table 748 QEI Interrupt Status register INTSTAT address 0x400C 6FE0 bit descrip...

Page 906: ...count 0 10 POS0REV_INT Combined position 0 and revolution count interrupt Set when both the POS0_INT bit is set and the REV0_INT is set 0 11 POS1REV_INT Combined position 1 and revolution count interr...

Page 907: ...ption Bit Symbol Description Reset value 0 INX_INT Indicates that an index pulse was detected 0 1 TIM_INT Indicates that a velocity timer overflow occurred 0 2 VELC_INT Indicates that captured velocit...

Page 908: ...725 When the SigMode bit 1 the quadrature decoder is bypassed and the PhA pin functions as the direction signal and PhB pin functions as the clock signal for the counters etc When the SigMode bit 0 th...

Page 909: ...abled Alternatively the phase signals can be interpreted as a clock and direction signal as output by some encoders The position counter is automatically reset on one of three conditions Incrementing...

Page 910: ...nd 4 for CapMode set to 1 For example consider a motor running at 600 rpm A 2048 pulse per revolution quadrature encoder is attached to the motor producing 8192 phase edges per revolution With clockin...

Page 911: ...nerated when the counter value equals the compare value after masking This allows for combinations not possible with a simple compare 32 4 General description The Repetitive Interrupt Timer RIT provid...

Page 912: ...T_INT 32 32 32 32 PBUS write 1 to clear PBUS PBUS PBUS CLR RESET PBUS PBUS PBUS CNT_ENA CTRL register CLR RESET ENABLE_CLK Table 756 Register overview Repetitive Interrupt Timer RIT base address 0x400...

Page 913: ...COMPVAL and MASK registers Writing a 1 to this bit will clear it to 0 Writing a 0 has no effect 0 The counter value does not equal the masked compare value 1 RITENCLR Timer enable clear 1 The timer w...

Page 914: ...LY causes the interrupt flag to be set It has no effect on the count sequence Counting continues as usual When the counter reaches 0xFFFFFFFF it rolls over to 0x000 00000 on the next clock and continu...

Page 915: ...d The alarm timer operates in the RTC power domain It consists of a 16 bit counter DOWNCOUNTER running at a 1024 Hz clock The 1024 Hz clock is derived from the 32 kHz crystal clock The alarm timer is...

Page 916: ...0xFDC Interrupt set enable register 0x0 Table 766 STATUS R 0xFE0 Status register 0x0 Table 767 ENABLE R 0xFE4 Enable register 0x0 Table 768 CLR_STAT W 0xFE8 Clear register 0x0 Table 769 SET_STAT W 0x...

Page 917: ...description Bit Symbol Description Reset value 0 STAT A 1 in this bit shows that the STATUS interrupt has been raised 0 31 1 Reserved Table 768 Interrupt enable register ENABLE 0x4004 0FE4 bit descrip...

Page 918: ...etween a minimum and maximum time out period both programmable Optional warning interrupt can be generated at a programmable time prior to watchdog time out Programmable 24 bit timer with internal fix...

Page 919: ...auses 0xFF to be loaded in the counter Hence the minimum Watchdog interval is TWDCLK 256 4 and the maximum Watchdog interval is TWDCLK 224 4 in multiples of TWDCLK 4 The Watchdog should be used in the...

Page 920: ...value of the counter on WDCLK and then synchronize it with the PCLK for reading when the TV register by the CPU 34 7 Register description The Watchdog registers are shown in Table 772 1 Reset value r...

Page 921: ...interrupt occurs in Sleep or Deep sleep mode it will wake up the device Table 773 Watchdog Mode register MOD 0x4008 0000 bit description Bit Symbol Value Description Reset value 0 WDEN Watchdog enabl...

Page 922: ...other than writing 0x55 to FEED register causes an immediate reset interrupt when the Watchdog is enabled and sets the WDTOF flag The reset will be generated during the second PCLK following an incor...

Page 923: ...nts 4 096 watchdog clocks for the interrupt to occur prior to a watchdog event If WDWARNINT is set to 0 the interrupt will occur at the same time as the watchdog event 34 7 6 Watchdog timer window reg...

Page 924: ...wn below in Figure 109 Table 779 Watchdog Timer Window register WINDOW 0x4008 0018 bit description Bit Symbol Description Reset value 23 0 WDWINDOW Watchdog window value 0xFF FFFF 31 24 Reserved user...

Page 925: ...LK 4 Watchdog Counter Early Feed Event Watchdog Reset Conditions WINDOW 0x1200 WARNINT 0x3FF TC 0x2000 Fig 110 Correct Watchdog Feed with Windowed Mode Enabled Correct Feed Event 1201 11FF 1200 WDCLK...

Page 926: ...s Measures the passage of time to maintain a calendar and clock Provides seconds minutes hours day of month month year day of week and day of year Ultra low power design to support battery powered sys...

Page 927: ...llator that produces a 1 Hz internal time reference The RTC is powered by its own power supply pin VBAT 35 5 Pin description Fig 112 RTC functional block diagram day of year second minute hour day mon...

Page 928: ...idated Time Register 1 1 Table 789 CTIME2 R 0x01C Consolidated Time Register 2 1 Table 790 SEC R W 0x020 Seconds Register 1 Table 793 MIN R W 0x024 Minutes Register 1 Table 794 HRS R W 0x028 Hours Reg...

Page 929: ...0 1 RTCALF When one the alarm registers generated an interrupt Writing a one to this bit location clears the alarm interrupt 0 31 2 Reserved user software should not write ones to reserved bits The va...

Page 930: ...d value generates an interrupt 0 1 IMMIN When 1 an increment of the Minute value generates an interrupt 0 2 IMHOUR When 1 an increment of the Hour value generates an interrupt 0 3 IMDOM When 1 an incr...

Page 931: ...tion Reset value 5 0 SECONDS Seconds value in the range of 0 to 59 1 7 6 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 13 8 MINUTES Mi...

Page 932: ...for leap years 1 31 12 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 791 Time Counter relationships and values Counter Size Enab...

Page 933: ...Minutes value in the range of 0 to 59 1 31 6 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined Table 795 Hours register HRS address 0x400...

Page 934: ...ts in this register are not changed by reset Table 798 Day of year register DOY address 0x4004 6034 bit description Bit Symbol Description Reset value 8 0 DOY Day of year value in the range of 1 to 36...

Page 935: ...er software should not write ones to reserved bits The value read from a reserved bit is not defined Table 801 Calibration register CALIBRATION address 0x4004 6040 bit description Bit Symbol Value Des...

Page 936: ...ue in the range of 1 to 28 29 30 or 31 depending on the month and whether it is a leap year 1 31 5 Reserved user software should not write ones to reserved bits The value read from a reserved bit is n...

Page 937: ...some typical voltage and temperature conditions without the need to externally trim the RTC oscillator A recommended method for determining the calibration value is to use the CLKOUT feature to unint...

Page 938: ...e cycle as the calibration match the alarm interrupt will be delayed by one cycle to avoid a double alarm interrupt Forward calibration Enable the RTC timer and calibration in the CCR register set bit...

Page 939: ...a dedicated counter tracking the total number of events Timestamp values are taken from the RTC Runs in RTC power domain independent of system power supply Can run in Deep Power Down mode if VBAT is...

Page 940: ...ms rejection filter in case of the 1 kHz sample clock a 15 6 31 2 ms rejection filter in case of the 64 Hz sample clock and a 62 5 125ms rejection filter in case of the 16 Hz sample clock Such an eve...

Page 941: ...should ignore the timestamp registers if the ERSTATUS EVx bit is cleared There is no mechanism to clear or invalidate the timestamps after the event flag in the status register has been cleared The ti...

Page 942: ...813 Register overview event monitor recorder base address 0x4004 6000 Name Access Address offset Description Reset value ERCONTROL R W 0x084 Event Monitor Recorder Control register Contains bits that...

Page 943: ...remain DISABLED when not being used for event detection particularly if the associated pin is being used for some other function 0 0 Event 0 input is disabled and forced high internally 1 Event 0 inpu...

Page 944: ...DE Controls enabling the Event Monitor Recorder and selecting its operating frequency Event Monitor Recorder registers can always be written to regardless of the state of these bits Events occurring d...

Page 945: ...Event flag WAKEUP1 pin Set at the end of any second if there has been an event during the preceding second This bit is cleared by writing a 1 to it Writing 0 has no effect 0 0 No event change on chan...

Page 946: ...n each Event Monitor Recorder channel Contents of these register are only valid if the corresponding EVx bit in the ERSTATUS register 1 Table 816 Event Monitor Recorder Counters Register ERCOUNTERS ad...

Page 947: ...event and the most recent event being the same The values will diverge if a second event occurs on the same channel Table 818 Event Monitor Recorder Last Stamp Register ERLASTSTAMP0 0x0x4004 60A0 ERL...

Page 948: ...the timers or the SCT In synchronous mode set the clock frequency on pin U0 2 3_UCLK to 6 BASE_UART0 2 3_CLK 37 3 Features 16 byte receive and transmit FIFOs Register locations conform to 550 industr...

Page 949: ...ccess by the CPU or host via the generic host interface The USART transmitter block TX accepts data written by the CPU or host and buffers the data in the USART TX Holding Register FIFO THR The USART...

Page 950: ...ter Shift Register Transmitter Holding Register Transmitter FIFO Transmitter Receiver Shift Register Receiver Buffer Register Receiver FIFO Receiver TX_DMA_REQ TX_DMA_CLR RX_DMA_REQ RX_DMA_CLR Transmi...

Page 951: ...Output Serial transmit data U3_DIR I O RS 485 EIA 485 output enable direction control U3_UCLK I O Serial clock input output for USART3 in synchronous mode U3_BAUD O USART3 baud output U3_BAUD is an ac...

Page 952: ...s for the auto baud feature 0x00 Table 833 ICR R W 0x024 IrDA control register USART3 only 0x00 Table 834 FDR R W 0x028 Fractional Divider Register Generates a clock input for the baud rate divider 0x...

Page 953: ...is always Write Only 37 6 3 USART Divisor Latch LSB and MSB Registers The USART Divisor Latch is part of the USART Baud Rate Generator and holds the value used along with the Fractional Divider to div...

Page 954: ...gister determines the baud rate of the USART 0x00 31 8 Reserved Table 826 USART Interrupt Enable Register when DLAB 0 IER addresses 0x4008 1004 USART0 0x400C 1004 USART2 0x400C 2004 USART3 bit descrip...

Page 955: ...bit description Bit Symbol Value Description Reset value Table 827 USART Interrupt Identification Register read only IIR addresses 0x4008 1008 USART0 0x400C 1008 USART2 0x400C 2008 USART3 bit descript...

Page 956: ...nterrupt IIR 3 1 010 shares the second level priority with the CTI interrupt IIR 3 1 110 The RDA is activated when the USART Rx FIFO reaches the trigger level defined in FCR7 6 and is reset when the U...

Page 957: ...at least two characters in the THR at one time since the last THRE 1 event This delay is provided to give the CPU time to write data to THR without a THRE interrupt to decode and service A THRE interr...

Page 958: ...08 USART2 0x400C 2008 USART3 bit description Bit Symbol Value Description Reset value 0 FIFOEN FIFO Enable 0 0 USART FIFOs are disabled Must not be used in the application 1 Active high enable for bot...

Page 959: ...WLS Word Length Select 0 0x0 5 bit character length 0x1 6 bit character length 0x2 7 bit character length 0x3 8 bit character length 2 SBS Stop Bit Select 0 0 1 stop bit 1 2 stop bits 1 5 if LCR 1 0 0...

Page 960: ...is dependent on FCR 0 Note A parity error is associated with the character at the top of the USART RBR FIFO 0 0 Parity error status is inactive 1 Parity error status is active 3 FE Framing Error When...

Page 961: ...T is cleared when either the TSR or the THR contain valid data 1 0 THR and or the TSR contains valid data 1 THR and the TSR are empty 7 RXFE Error in RX FIFO LSR 7 is set when a character with a RX er...

Page 962: ...bit This bit is automatically cleared after auto baud completion 1 MODE Auto baud mode select bit 0 0 Mode 0 1 Mode 1 2 AUTORESTART Restart bit 0 0 No restart 1 Restart in case of time out counter re...

Page 963: ...ck according to the specified fractional requirements Important If the fractional divider is active DIVADDVAL 0 and DLM 0 the value of the DLL register must be 3 or greater 1 IRDAINV Serial input dire...

Page 964: ...two requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided 37 6 13 USART Oversampling Register In most...

Page 965: ...ensures that the receiver is locked when idle or will enter a locked state after having received a complete ongoing character reception Line conflicts must be handled in software The behavior of the U...

Page 966: ...USART2 0x400C 2048 USART3 bit description Bit Symbol Value Description Reset value 0 SCIEN Smart Card Interface Enable 0 0 Smart card interface disabled 1 Asynchronous half duplex smart card interfac...

Page 967: ...process the information before sending a response The extra guard time can be programmed from 0 to 255 where 255 indicates the minimum possible character length This value is depending on the selected...

Page 968: ...are a received address value to During automatic address detection this value is used to accept or reject serial input data 3 Reserved 4 DCTRL Direction control for DIR pin 0 0 Disable Auto Direction...

Page 969: ...rection control delay value This register works in conjunction with an 8 bit counter 0x00 31 8 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not d...

Page 970: ...ped by hardware after having received a complete character This can be done by asserting the CCCLR bit This is useful in half duplex mode where the clock cannot be generated by sending a character Aft...

Page 971: ...ACR Mode bit In Mode 0 the baud rate is measured on two subsequent falling edges of the USART Rx pin the falling edge of the start bit and the falling edge of the least significant bit In Mode 1 the b...

Page 972: ...l execute the following phases 1 On ACR Start bit setting the baud rate measurement counter is reset and the USART RSR is reset The RSR baud rate is switched to the highest rate 2 A falling edge on US...

Page 973: ...algorithm illustrates one way of finding a set of DLM DLL MULVAL and DIVADDVAL values Such set of parameters yields a baud rate with a relative error of less than 1 1 from the desired one a Mode 0 st...

Page 974: ...37 LPC43xx USART0_2_3 Fig 116 Algorithm for setting USART dividers PCLK BR Calculating UART baudrate BR DL est PCLK 16 x BR DLest is an integer DIVADDVAL 0 MULVAL 1 True FR est 1 5 DL est Int PCLK 16...

Page 975: ...DIVADDVAL 5 and MULVAL 8 According to Equation 6 the USART s baud rate is 115384 This rate has a relative error of 0 16 from the originally specified 115200 37 7 4 RS 485 EIA 485 modes of operation T...

Page 976: ...le the receiver RS 485 EIA 485 Auto Address Detection AAD mode When both RS485CTRL register bits 0 9 bit mode enable and 2 AAD mode enable are set the USART is in auto address detect mode In this mode...

Page 977: ...r allows to control The direction of the serial clock i e synchronous slave or master mode The sampling edge of the serial clock Two stage or one stage synchronization of the input serial clock during...

Page 978: ...ed by the slave is stable before this rising edge the external slave clock In this way it is ensured that the master receives as many bits as it has transmitted When the first sample edge of the incom...

Page 979: ...rt card reset and power pins Any power supplied to the card must be externally switched as card power supply requirements often exceed source currents possible on this part As the specific application...

Page 980: ...t rather to maintain a fraction of the previously mentioned clock rate For example if the clock rate is set to 4 MHz the baud rate would be 10753 A clock rate of 3 5712 MHz would need a baud rate of 9...

Page 981: ...m control handshaking available Data sizes of 5 6 7 and 8 bits Parity generation and checking odd even mark space or none One or two stop bits 16 byte Receive and Transmit FIFOs Built in baud rate gen...

Page 982: ...er FIFO THR The UART1 TX Shift Register TSR reads the data stored in the THR and assembles the data to transmit via the serial output pin TXD1 The UART1 Baud Rate Generator block BRG generates the tim...

Page 983: ...nsmitter Holding Register Transmitter FIFO Transmitter Receiver Shift Register Receiver Buffer Register Receiver FIFO Receiver TX_DMA_REQ TX_DMA_CLR RX_DMA_REQ RX_DMA_CLR Baud Rate Generator Fractiona...

Page 984: ...ority level 4 interrupt if enabled IER 3 1 U1_DSR Input Data Set Ready Active low signal indicates if the external modem is ready to establish a communications link with the UART1 In normal operation...

Page 985: ...r Contains individual interrupt enable bits for the 7 potential UART1 interrupts DLAB 0 0x00 Table 853 IIR RO 0x008 Interrupt ID Register Identifies which interrupt s are pending 0x01 Table 854 FCR WO...

Page 986: ...the THR The THR is write only 38 6 3 UART1 Divisor Latch LSB and MSB Registers when DLAB 1 The UART1 Divisor Latch is part of the UART1 Baud Rate Generator and holds the value used along with the Frac...

Page 987: ...e UART1 0x00 31 8 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 853 UART1 Interrupt Enable Register when DLAB 0 IER address 0...

Page 988: ...BEOIE Enables the end of auto baud interrupt 0 0 Disable end of auto baud Interrupt 1 Enable end of auto baud Interrupt 9 ABTOIE Enables the auto baud time out interrupt 0 0 Disable auto baud time out...

Page 989: ...n FCR7 6 and is reset when the UART1 Rx FIFO depth falls below the trigger level When the RDA interrupt goes active the CPU can read a block of data defined by the trigger level The CTI interrupt IIR...

Page 990: ...y the THR is empty The THRE interrupt is reset when a THR write occurs or a read of the IIR occurs and the THRE is the highest interrupt IIR 3 1 001 It is the lowest priority interrupt and is activate...

Page 991: ...Control Register The LCR determines the format of the data character that is to be transmitted or received 1 RXFIFORES RX FIFO Reset 0 0 No impact on either of UART1 FIFOs 1 Writing a logic 1 to FCR...

Page 992: ...er and the attached parity bit will be odd 0x1 Even Parity Number of 1s in the transmitted character and the attached parity bit will be even 0x2 Forced 1 stick parity 0x3 Forced 0 stick parity 6 BC B...

Page 993: ...R 0 0 Disable modem loopback mode 1 Enable modem loopback mode 5 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 0 6 RTSEN RTS enable 0...

Page 994: ...the spacing state all zeroes for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to m...

Page 995: ...f input CTS Cleared on an MSR read 0 0 No change detected on modem input CTS 1 State change detected on modem input CTS 1 DDSR Delta DSR Set upon state change of input DSR Cleared on an MSR read 0 0 N...

Page 996: ...ning Auto baud run bit This bit is automatically cleared after auto baud completion 1 MODE Auto baud mode select bit 0 0 Mode 0 1 Mode 1 2 AUTORESTART Auto baud restart bit 0 0 No restart 1 Restart in...

Page 997: ...o then the fractional divider is disabled and the clock will not be divided 38 6 14 UART1 Transmit Enable Register In addition to being equipped with full hardware flow control auto cts and auto rts m...

Page 998: ...ser software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 865 UART1 RS485 Control register RS485CTRL address 0x4008 204C bit description Bit Symbol...

Page 999: ...o a high value It is possible that the sending UART sends an additional byte after the trigger level is reached assuming the sending UART has another byte to send because it might not recognize the de...

Page 1000: ...CTS mode a change of the CTS1 signal does not trigger a modem status interrupt unless the CTS Interrupt Enable bit is set Delta CTS bit in the MSR will be set though Table 868 lists the conditions fo...

Page 1001: ...nding transmission has completed The UART will continue transmitting a 1 bit as long as CTS1 is de asserted high As soon as CTS1 gets de asserted transmission resumes and a start bit is sent followed...

Page 1002: ...nsmit and receive 4 bit to 16 bit frame 39 4 General description The SSP is a Synchronous Serial Port SSP controller capable of operation on a SPI 4 wire SSI or Microwire bus It can interact with mult...

Page 1003: ...rding to the protocol in use When there is just one bus master and one bus slave the Frame Sync or Slave Select signal from the Master can be connected directly to the slave s corresponding input When...

Page 1004: ...4 SSP0 DMA control register 0 Table 882 Table 871 Register overview SSP0 base address 0x4008 3000 Name Access Address offset Description Reset value 1 Reference Table 872 Register overview SSP1 base a...

Page 1005: ...ansfer 0xF 16 bit transfer 5 4 FRF Frame Format 00 0x0 SPI 0x1 TI 0x2 Microwire 0x3 This combination is not supported and should not be used 6 CPOL Clock Out Polarity This bit is only used in SPI mode...

Page 1006: ...OD Slave Output Disable This bit is relevant only in slave mode MS 1 If it is 1 this blocks this SSP controller from driving the transmit data line MISO 0 31 4 Reserved user software should not write...

Page 1007: ...asked in the opposite sense from classic computer terminology in which masked meant disabled ARM uses the word masked to mean enabled To avoid confusion we will not use the word masked Table 876 SSP S...

Page 1008: ...e out condition occurs A Receive Time out occurs when the Rx FIFO is not empty and no has not been read for a time out period The time out period is the same for master and slave modes and is determin...

Page 1009: ...is 1 if the Rx FIFO is not empty has not been read for a time out period and this interrupt is enabled The time out period is the same for master and slave modes and is determined by the SSP bit rate...

Page 1010: ...ing edge of CLK the MSB of the 4 bit to 16 bit data frame is shifted out on the DX pin Likewise the MSB of the received data is shifted onto the DR pin by the off chip serial slave device Table 882 SS...

Page 1011: ...ol bit is 0 it produces a steady state low value on the SCK pin If the CPOL clock polarity control bit is 1 a steady state high value is placed on the CLK pin when data is not being transferred The CP...

Page 1012: ...sion after all bits of the data word have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured However in the case of continuous back t...

Page 1013: ...e word transfer after all bits have been transferred the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured For continuous back to back transfers the SSEL...

Page 1014: ...er This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the CPHA bit is logic zero Therefore the master device must raise the...

Page 1015: ...chip slave device During this transmission no incoming data is received by the SSP After the message has been sent the off chip slave decodes it and after waiting one serial clock after the last bit...

Page 1016: ...data from the current frame Each of the received values is transferred from the receive shifter on the falling edge SK after the LSB of the frame has been latched into the SSP 39 7 3 1 Setup and hold...

Page 1017: ...s per transfer 40 4 General description SPI is a full duplex serial interface It can handle multiple masters and slaves being connected to a given bus Only a single master and a single slave can commu...

Page 1018: ...ev 1 3 6 July 2012 1018 of 1269 NXP Semiconductors UM10503 Chapter 40 LPC43xx SPI Fig 130 SPI block diagram MOSI_IN MOSI_OUT MISO_IN MISO_OUT OUTPUT ENABLE LOGIC SPI REGISTER INTERFACE SPI Interrupt A...

Page 1019: ...al is not directly driven by the master It could be driven by a simple general purpose I O under software control Remark Note that this pin in an input pin only The SPI in master mode cannot drive the...

Page 1020: ...Description Reset value 1 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined 2 BITENABLE 0 The SPI controller sends and receives 8 bits...

Page 1021: ...4 bits per transfer 0xF 15 bits per transfer 0x0 16 bits per transfer 31 12 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 886...

Page 1022: ...of the SPCCR register is not relevant 6 WCOL Write collision When 1 this bit indicates that a write collision has occurred This bit is cleared by reading this register then accessing the SPI Data Reg...

Page 1023: ...010 bit description Bit Symbol Description Reset value 7 0 COUNTER SPI0 Clock counter setting 0x00 31 8 Reserved user software should not write ones to reserved bits The value read from a reserved bit...

Page 1024: ...e two points First the SPI is illustrated with the Clock Polarity control bit CPOL in the SPI Control Register set to both 0 and 1 The second point to note is the activation and de activation of the S...

Page 1025: ...tive When a device is a slave and CPHA is set to 1 the transfer starts on the first clock edge when the slave is selected and ends on the last clock edge where data is sampled Fig 131 SPI data transfe...

Page 1026: ...hen a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data buffer where it is later read A read of the SPI Data...

Page 1027: ...hen a slave SPI transfer is not in progress 3 Wait for the SPIF bit in the SPI Status Register to be set to 1 The SPIF bit will be set after the last sampling clock edge of the SPI data transfer 4 Rea...

Page 1028: ...cted the device to be a slave This condition is known as a mode fault When a mode fault is detected the mode fault MODF bit in the SPI Status Register will be activated the SPI signal drivers will be...

Page 1029: ...rough the GIMA see Table 148 41 3 Features The I2S bus provides a standard communication interface for digital audio applications The I2S bus specification defines a 3 wire serial bus having one data...

Page 1030: ...red by FIFOs with a depth of 8 words The I2S receive and transmit stage can operate independently in either slave or master mode In master mode the I2S module supplies the SCK and WS signals In slave...

Page 1031: ...S blocks in slave and master mode to capture or generate data MWS either originates either from the pin mux SCU in slave mode the I2S_WS signal or is generated by the I2S block in master mode The MWS...

Page 1032: ...B first It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the I2S bus specification I2S0 1_RX_MCLK Output Optional master clock output for the I2S receive functi...

Page 1033: ...pter 41 LPC43xx I2S interface Fig 133 Simple I2S configurations and bus timing TRANSMITTER MASTER CONTROLLER MASTER TRANSMITTER SLAVE RECEIVER MASTER SCK serial clock WS word select SD serial data TRA...

Page 1034: ...Register Contains status information about the I2S interface 0x7 Table 902 DMA1 R W 0x014 I2S DMA Configuration Register 1 Contains control information for DMA request 1 0 Table 903 DMA2 R W 0x018 I2S...

Page 1035: ...ol information for DMA request 2 0 Table 904 IRQ R W 0x01C I2S Interrupt Request Control Register Contains bits that control how the I2S interrupt request is generated 0 Table 905 TXRATE R W 0x020 I2S...

Page 1036: ...ts The value read from a reserved bit is not defined Table 898 I2S Digital Audio Output register DAO address 0x400A 2000 I2S0 and 0x400A 3000 I2S1 bit description Bit Symbol Value Description Reset va...

Page 1037: ...nsmit Interrupt This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register 1 1 DMAREQ1 This bit reflects the presence of Receive or Transmi...

Page 1038: ...rite ones to reserved bits The value read from a reserved bit is not defined Table 903 I2S DMA Configuration register 1 DMA1 address 0x400A 2014 I2S0 and 0x400A 3014 I2S1 bit description Bit Symbol De...

Page 1039: ...e clock Therefore the output jitter will not be greater than plus or minus one source clock between consecutive clock edges For example if X 0x07 and Y 0x11 the fractional rate generator will output 7...

Page 1040: ...lso the value of Y must be greater than or equal to X 41 6 11 I2S Transmit Clock Bit Rate register The bit rate for the I2S transmitter is determined by the value of the TXBITRATE register The value d...

Page 1041: ...d how MCLK is used Table 909 I2S Receive Clock Rate register RXBITRATE address 0x400A 202C I2S0 and 0x400A 302C I2S1 bit description Bit Symbol Description Reset value 5 0 RX_BITRATE I2S receive bit r...

Page 1042: ...he WORDWIDTH value in the configuration register see Table 898 There is a separate WORDWIDTH value for the receive channel and the transmit channel tbd shows the possible data sequences 0 word is cons...

Page 1043: ...S is high received data is expected to be right data Reception will stop when the bit counter has reached the limit set by the WORDWIDTH value On the next change of WS the received data will be stored...

Page 1044: ...Chapter 41 LPC43xx I2S interface CREG6 bits 12 and 13 select PLL0AUDIO for the I2S0 interface CREG bits 14 and 15 select PLL0AUDIO for the I2S1 interface Fig 134 I2S clocking and pin connections I2 S...

Page 1045: ...The I2S transmit function operates as a master The transmit clock source TX_MCLK is derived from PCLK using the fractional divider The WS used is the internally generated TX_WS The TX_MCLK pin is not...

Page 1046: ...ved from PCLK using the fractional divider The WS used is the internally generated TX_WS The TX_MCLK pin is enabled for output Bold lines indicate the clock path for this configuration CREG6 bits 12 a...

Page 1047: ...clock RX_MCLK The I2S transmit function operates as a master The transmit clock source is RX_MCLK The WS used is the internally generated TX_WS The TX_MCLK pin is not enabled for output Bold lines ind...

Page 1048: ...SCK is provided by the external master on the TX_SCK pin The transmit bit rate divider must be set to 1 TXBITRATE 5 0 000000 for this mode to operate correctly The WS signal is provided by the externa...

Page 1049: ...function The receive function can operate in either master or slave mode determining the operating mode of the entire I2S interface The transmit clock source is RX_SCK The WS used is the internally g...

Page 1050: ...the output of the Audio PLL PLLAUDIO The WS used is the internally generated TX_WS The TX_MCLK pin is enabled for output Bold lines indicate the clock path for this configuration CREG6 bits 12 and 13...

Page 1051: ...y the external master on the TX_MCLK pin The WS used is the internally generated TX_WS The TX_MCLK pin is enabled for input Bold lines indicate the clock path for this configuration CREG6 bits 12 and...

Page 1052: ...eive function operates as a master The receive clock source RX_MCLK is derived from PCLK using the fractional divider The WS used is the internally generated RX_WS The RX_MCLK pin is not enabled for o...

Page 1053: ...from PCLK using the fractional divider The WS used is the internally generated RX_WS The RX_MCLK pin is enabled for output Bold lines indicate the clock path for this configuration CREG6 bits 12 and 1...

Page 1054: ...clock TX_MCLK The I2S receive function operates as a master The receive clock source is TX_MCLK The WS used is the internally generated RX_WS The RX_MCLK pin is not enabled for output Bold lines indi...

Page 1055: ...is provided by the external master on the RX_SCK pin The receive bit rate divider must be set to 1 RXBITRATE 5 0 000000 for this mode to operate correctly The WS signal is provided by the external ma...

Page 1056: ...function The transmit function can operate in either master or slave mode determining the operating mode of the entire I2S interface The receive clock source is TX_SCK The WS used is the internally ge...

Page 1057: ...output of the Audio PLL PLLAUDIO The WS used is the internally generated RX_WS The RX_MCLK pin is enabled for output Bold lines indicate the clock path for this configuration CREG6 bits 12 and 13 sel...

Page 1058: ...MCLK CREG bit 13 DAI bit 5 RXMODE bits 3 0 Description 0 0 0 0 0 1 Receiver master mode The I2S receive function operates as a master The receive clock source RX_MCLK is provided by the external mast...

Page 1059: ...th_dma1 tx_level dmareq_rx_1 rx_depth_dma1 rx_level dmareq_tx_2 tx_depth_dma2 tx_level dmareq_rx_2 rx_depth_dma2 rx_level irq_tx tx_depth_irq tx_level irq_rx rx_depth_irq rx_level Table 927 DMA and in...

Page 1060: ...ductors UM10503 Chapter 41 LPC43xx I2S interface Fig 149 FIFO contents for various I2S modes LEFT 1 7 0 RIGHT 1 7 0 LEFT 7 0 RIGHT 7 0 Stereo 8 bit data mode N 3 7 0 N 2 7 0 N 1 7 0 N 7 0 Mono 8 bit d...

Page 1061: ...o the C_CAN0 and C_CAN1 interfaces can be set independently of each other 42 3 Features Conforms to protocol version 2 0 parts A and B Supports bit rate of up to 1 Mbit s Supports 32 Message Objects E...

Page 1062: ...core message RAM a message handler control registers and the APB interface For communication on a CAN network individual Message Objects are configured The Message Objects and Identifier Masks for acc...

Page 1063: ...XP B V 2012 All rights reserved User manual Rev 1 3 6 July 2012 1063 of 1269 NXP Semiconductors UM10503 Chapter 42 LPC43xx C_CAN 42 5 Pin description Table 930 C_CAN pin description Pin function Direc...

Page 1064: ...scaler extension register 0x0000 Table 939 0x01C Reserved IF1_CMDREQ R W 0x020 Message interface 1 command request 0x0001 Table 942 IF1_CMDMSK_W R W 0x024 Message interface 1 command mask write direct...

Page 1065: ...970 IR2 RO 0x144 Interrupt pending 2 0x0000 Table 971 0x148 0x15C Reserved MSGV1 RO 0x160 Message valid 1 0x0000 Table 972 MSGV2 RO 0x164 Message valid 2 0x0000 Table 973 0x168 0x17C Reserved CLKDIV R...

Page 1066: ...W 0x084 Message interface 2 command mask read direction 0x0000 Table 947 IF2_MSK1 R W 0x088 Message interface 2 mask 1 0xFFFF Table 949 IF2_MSK2 R W 0x08C Message interface 2 mask 2 0xFFFF Table 951 I...

Page 1067: ...address 0x400E 2000 C_CAN0 and 0x400A 4000 C_CAN1 bit description Bit Symbol Value Description Reset value Access 0 INIT Initialization 1 R W 0 Normal operation 1 Initialization is started On reset so...

Page 1068: ...recovery sequence the Error Management Counters will be reset During the waiting time after the resetting of INIT each time a sequence of 11 HIGH recessive bits has been monitored a Bit0Error code is...

Page 1069: ...logical value 1 but the monitored bus value was LOW dominant 0x5 Bit0Error During the transmission of a message or acknowledge bit or active error flag or overload flag the device wanted to send a LO...

Page 1070: ...ification 6 EWARN Warning status 0 RO 0 Both error counters are below the error warning limit of 96 1 At least one of the error counters in the EC has reached the error warning limit of 96 7 BOFF Buso...

Page 1071: ...pt has the highest priority Among the message interrupts the Message Object s interrupt priority decreases with increasing message number A message interrupt is cleared by clearing the Message Object...

Page 1072: ...r 3 SILENT Silent mode 0 R W 0 Normal operation 1 The module is in silent mode 4 LBACK Loop back mode 0 R W 0 Loop back mode is disabled 1 Loop back mode is enabled 6 5 TX1_0 Control of TD pins 00 R W...

Page 1073: ...om the Message RAM allowing both processes to be interrupted by each other Each set of interface registers consists of message buffer registers controlled by their own command registers The command ma...

Page 1074: ...atically set to 1 and the signal CAN_WAIT_B is pulled LOW to notify the CPU that a transfer is in progress After a wait time of 3 to 6 CAN_CLK periods the transfer between the Interface Register and t...

Page 1075: ...lected for data transfer 0x00 Not a valid message number This value is interpreted as 0x20 1 0x21 to 0x3F Not a valid message number This value is interpreted as 0x01 0x1F 1 0x01 R W 14 6 Reserved 15...

Page 1076: ...essage interface command mask registers write direction IF1_CMDMSK_W address 0x400E 2024 C_CAN0 and 0x400A 4024 C_CAN1 bit description Bit Symbol Value Description Reset value Access 0 DATA_B Access d...

Page 1077: ...4 7 unchanged 1 Transfer data bytes 4 7 to message object 1 DATA_A Access data bytes 0 3 0 R W 0 Data bytes 0 3 unchanged 1 Transfer data bytes 0 3 to message object 2 TXRQST Access transmission requ...

Page 1078: ...4 7 unchanged 1 Transfer data bytes 4 7 to IFx message buffer register 1 DATA_A Access data bytes 0 3 0 R W 0 data bytes 0 3 unchanged 1 Transfer data bytes 0 3 to IFx message buffer 2 NEWDAT Access n...

Page 1079: ...et value Access 0 DATA_B Access data bytes 4 7 0 R W 0 data bytes 4 7 unchanged 1 Transfer data bytes 4 7 to IFx message buffer register 1 DATA_A Access data bytes 0 3 0 R W 0 data bytes 0 3 unchanged...

Page 1080: ...eserved 0 Table 947 CAN message interface command mask registers read direction IF2_CMDMSK_R address 0x400E 2084 C_CAN0 and 0x400A 4084 C_CAN1 bit description continued Bit Symbol Value Description Re...

Page 1081: ...tion bit DIR is used for acceptance filtering 15 MXTD Mask extend identifier 1 R W 0 The extended identifier bit IDE has no effect on acceptance filtering 1 The extended identifier bit IDE is used for...

Page 1082: ...0 ID15_0 Message identifier 29 bit identifier extended frame 11 bit identifier standard frame 0x00 R W 31 16 Reserved 0 Table 954 CAN message interface command arbitration 2 registers IF1_ARB2 address...

Page 1083: ...N0 and 0x400A 4094 C_CAN1 bit description Bit Symbol Value Description Reset value Access 12 0 ID28_16 Message identifier 29 bit identifier extended frame 11 bit identifier standard frame 0x00 R W 13...

Page 1084: ...nued Bit Symbol Value Description Reset value Access Table 956 CAN message interface message control registers IF1_MCTRL address 0x400E 2038 C_CAN0 and 0x400A 4038 C_CAN1 bit description Bit Symbol Va...

Page 1085: ...13 INTPND Interrupt pending 0 R W 0 This message object is not the source of an interrupt 1 This message object is the source of an interrupt The Interrupt Identifier in the Interrupt Register will p...

Page 1086: ...FIFO buffer and is not the last message object of that FIFO buffer 1 Single message object or last message object of a FIFO buffer 8 TXRQST Transmit request 0 R W 0 This message object is not waiting...

Page 1087: ...rce of an interrupt The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority 14 MSGLST Message lost only valid fo...

Page 1088: ...A3 Data byte 3 0x00 R W 31 16 Reserved Table 961 CAN message interface data A2 registers IF2_DA2 address 0x400E 20A0 C_CAN0 and 0x400A 40A0 C_CAN1 bit description Bit Symbol Description Reset value Ac...

Page 1089: ...age Object a Transmission Request is pending The TXRQST bit of a specific Message Object can be set reset by the CPU via the IFx Message Interface Registers or by the Message Handler after reception o...

Page 1090: ...cts 16 to 1 By reading out the INTPND bits the CPU can check for which Message Object an interrupt is pending The INTPND bit of a specific Message Object can be set reset by the CPU via the IFx Messag...

Page 1091: ...to 17 By reading out the MSGVAL bits the CPU can check which Message Object is valid The MSGVAL bit of a specific Message Object can be set reset by the CPU via the IFx Message Interface Registers Tab...

Page 1092: ...INIT to 0 The data stored in the message RAM is not affected by a hardware reset After power on the contents of the message RAM is undefined Table 973 CAN message valid 2 register MSGV2 address 0x400...

Page 1093: ...ation of the Message Objects is independent of INIT and also can be done on the fly but the Message Objects should all be configured to particular identifiers or set to not valid during software initi...

Page 1094: ...tomatic Retransmission mode is enabled by programming bit DAR in the CAN Control Register to one In this operation mode the programmer has to consider the different behavior of bits TXRQST and NEWDAT...

Page 1095: ...the acknowledge slot of a data remote frame in Loop back mode In this mode the CAN core performs an internal feedback from its CAN_TD output to its CAN_RD input The actual value of the CAN_RD input p...

Page 1096: ...he CPU has reset the BUSY bit a possible retransmission in case of lost arbitration or in case of an error is disabled The IF2 Registers are used as Receive Buffer After the reception of a message the...

Page 1097: ...ark The three test functions for pin CAN_TD interfere with all CAN protocol functions The CAN_TD pin must be left in its default function when CAN message transfer or any of the test modes Loo back mo...

Page 1098: ...leared the CAN Protocol Controller state machine of the CAN core and the Message Handler State Machine control the CAN controller s internal data flow Received messages that pass the acceptance filter...

Page 1099: ...e cell is ready for loading and if there is no data transfer between the IFx Registers and Message RAM the MSGVAL bits in the Message Valid Register TXRQST bits in the Transmission Request Register ar...

Page 1100: ...ote Frame while the requested Data Frame has just been received 42 7 3 4 2 Reception of a remote frame When a Remote Frame is received three different configurations of the matching Message Object hav...

Page 1101: ...gisters Neither MSGVAL nor TXRQST have to be reset before the update Even if only a part of the data bytes are to be updated all four bytes of the corresponding IFx Data A Register or IFx Data B Regis...

Page 1102: ...he IFx Interface registers The data consistency is guaranteed by the Message Handler state machine To transfer the entire received message from message RAM into the message buffer software must write...

Page 1103: ...into a Message Object of this FIFO Buffer starting with the Message Object with the lowest message number When a message is stored into a Message Object of a FIFO Buffer the NEWDAT bit of this Message...

Page 1104: ...nterrupt with the highest priority disregarding their chronological order An interrupt remains pending until the CPU has cleared it Fig 156 Reading a message from the FIFO buffer to the message buffer...

Page 1105: ...essage Objects where INTID points to the pending message interrupt with the highest interrupt priority The CPU controls whether a change of the Status Register may cause an interrupt bits EIE and SIE...

Page 1106: ...the Baud Rate Prescaler BRP tq BRP fsys The C_CAN s system clock fsys is the frequency C_CAN peripheral clock The Synchronization Segment Sync_Seg is the part of the bit time where edges of the CAN bu...

Page 1107: ...ormation provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 1 3 6 July 2012 1107 of 1269 NXP Semiconductors UM10503 Chapter 42 LPC43xx C_CAN Fig...

Page 1108: ...ed as Master Slave or Master Slave Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus Programmable clock allows adjustment of I2C transfer...

Page 1109: ...d by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than t...

Page 1110: ...Name Access Address offset Description Reset value 1 Reference CONSET R W 0x000 I2C Control Set Register When a one is written to a bit of this register the corresponding bit in the I2C control regis...

Page 1111: ...ation of the I2C interface in slave mode and is not used in master mode The least significant bit determines whether a slave responds to the General Call address 0x00 Table 990 DATA_BUFFER RO 0x02C Da...

Page 1112: ...ether determine the clock frequency generated by an I2C master and certain times used in slave mode 0x04 Table 987 CONCLR WO 0x018 I2C Control Clear Register When a one is written to a bit of this reg...

Page 1113: ...aster mode and transmit a START condition or transmit a Repeated START condition if it is already in master mode MASK1 R W 0x034 I2C Slave address mask register 1 This mask register is associated with...

Page 1114: ...STOP condition STO is cleared automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a ST...

Page 1115: ...een received the first bit of received data is located at the MSB of DAT 43 7 4 I2C Slave Address register 0 This register is readable and writable and are only used when an I2C interface is set to sl...

Page 1116: ...values SCLL and SCLH values should not necessarily be the same Software can set different duty cycles on SCL by setting these two registers For example the I2C bus specification defines the SCL low t...

Page 1117: ...ter Writing 0 has no effect I2ENC is the I2C Interface Disable bit Writing a 1 to this bit clears the I2EN bit in the CONSET register Writing 0 has no effect 43 7 7 I2C Monitor mode control register T...

Page 1118: ...abled 1 The I2C module will enter monitor mode In this mode the SDA output will be forced high This will prevent the I2C module from outputting data of any kind including ACK onto the I2C data bus Dep...

Page 1119: ...When this bit is set the General Call address 0x00 is recognized If these registers contain 0x00 the I2C will not acknowledge any address on the bus All four registers including ADR0 see Table 985 wi...

Page 1120: ...to determine what the received address was that actually caused the match 43 8 I2C operating modes In a given application the I2C block may operate as a master a slave or both In the slave mode the I...

Page 1121: ...is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The I2C interface will enter master transmitter mode when software sets the STA bit The I2C...

Page 1122: ...er mode the possible status codes are 0x40 0x48 or 0x38 For slave mode the possible status codes are 0x68 0x78 or 0xB0 For details refer to Table 999 After a Repeated START condition I2C may switch to...

Page 1123: ...this mode the direction bit will be 1 indicating a read operation Serial data is transmitted via SDA while the serial clock is input through SCL START and STOP conditions are recognized as the beginni...

Page 1124: ...2C bus interface 43 9 I2C implementation and operation Figure 164 shows how the on chip I2C bus interface is implemented and the following text describes the individual blocks Fig 163 Format of Slave...

Page 1125: ...l pad designed to conform to the I2C specification Fig 164 I2C serial interface block diagram APB BUS STATUS REGISTER I2CnSTAT CONTROL REGISTER and SCL DUTY CYLE REGISTERS I2CnCONSET I2CnCONCLR I2CnSC...

Page 1126: ...eived 8 bit byte with the General Call address 0x00 If an equality is found the appropriate status bits are set and an interrupt is requested 43 9 5 Shift register DAT This 8 bit register contains a b...

Page 1127: ...clock pulse generator provides the SCL clock pulses when the I2C block is in the master transmitter or master receiver mode It is switched off when the I2C block is in slave mode The I2C output clock...

Page 1128: ...rrespond to ones in the value written Conversely writing to CONCLR will clear bits in the I2C control register that correspond to ones in the value written 43 9 10 Status decoder and status register T...

Page 1129: ...from Table 998 to Table 1004 43 10 1 Master Transmitter mode In the master transmitter mode a number of data bytes are transmitted to a slave receiver see Figure 167 Before the master transmitter mod...

Page 1130: ...the interrupt service routine to enter the appropriate state service routine that loads DAT with the slave address and the data direction bit SLA W The SI bit in CON must then be reset before the ser...

Page 1131: ...ved Load data byte or 0 0 0 X Data byte will be transmitted ACK bit will be received No DAT action or 1 0 0 X Repeated START will be transmitted No DAT action or 0 1 0 X STOP condition will be transmi...

Page 1132: ...OR A A other Master continues other Master continues A other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Data byte Not Acknowledge received after...

Page 1133: ...ne must load DAT with the 7 bit slave address and the data direction bit SLA R The SI bit in CON must then be cleared before the serial transfer can continue When the slave address and the data direct...

Page 1134: ...bus becomes free 0x40 SLA R has been transmitted ACK has been received No DAT action or 0 0 0 0 Data byte will be received NOT ACK bit will be returned No DAT action 0 0 0 1 Data byte will be receive...

Page 1135: ...A OR A A P other Master continues other Master continues A other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H arbitration lost in Slave address or Acknowledge bit Not Acknowledge received aft...

Page 1136: ...own slave address followed by the data direction bit which must be 0 W for the I2C block to operate in the slave receiver mode After its own slave address and the W bit have been received the serial i...

Page 1137: ...o DAT action or X 0 0 0 Data byte will be received and NOT ACK will be returned No DAT action X 0 0 1 Data byte will be received and ACK will be returned 0x80 Previously addressed with own SLV address...

Page 1138: ...address will be recognized if ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or Repeated START condition has been received while still addressed as...

Page 1139: ...ore Data bytes arbitration lost as Master and addressed as Slave last data byte received is Not acknowledged arbitration lost as Master and addressed as Slave by General Call reception of the own Slav...

Page 1140: ...and a valid status code can be read from STAT This status code is used to vector to a state service routine and the appropriate action to be taken for each of these status codes is detailed in Table 1...

Page 1141: ...T ACK has been received No DAT action or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No DAT action or 0 0 0 1 Switched to not addressed SLV mode Own SL...

Page 1142: ...en a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit A...

Page 1143: ...START condition see Figure 171 Until this occurs arbitration is not lost by either master since they were both transmitting the same data If the I2C hardware detects a Repeated START condition on the...

Page 1144: ...for an uncontrolled source to cause a bus hang up In such situations the problem may be caused by interference temporary interruption of the bus or a temporary short circuit between SDA and SCL If an...

Page 1145: ...zation so a START should be generated to insure that all I2C peripherals are synchronized 43 10 6 5 Bus error A bus error occurs when a START or STOP condition is detected at an illegal position in th...

Page 1146: ...10 9 I2C interrupt service When the I2C interrupt is entered STAT contains a status code which identifies one of the 26 state services to be executed 43 10 10 The state service routines Each state rou...

Page 1147: ...ive buffer 5 Initialize the Master data counter to match the length of the message to be received 6 Exit 43 11 4 I2C interrupt routine Determine the I2C state and which state routine will be used to h...

Page 1148: ...State 10 Slave Address Write has been transmitted ACK has been received The first data byte will be transmitted an ACK bit will be received 1 Load DAT with first data byte from Master Transmit buffer...

Page 1149: ...SET to set the STA and AA bits 2 Write 0x08 to CONCLR to clear the SI flag 3 Exit 43 11 7 Master Receive states 43 11 7 1 State 0x40 Previous state was State 08 or State 10 Slave Address Read has been...

Page 1150: ...Write has been received ACK has been returned Data will be received and ACK returned 1 Write 0x04 to CONSET to set the AA bit 2 Write 0x08 to CONCLR to clear the SI flag 3 Set up Slave Receive mode da...

Page 1151: ...d Additional data will be read 1 Read data byte from DAT into the Slave Receive buffer 2 Decrement the Slave data counter skip to step 5 if not the last data byte 3 Write 0x0C to CONCLR to clear the S...

Page 1152: ...ave Address Read has been received ACK has been returned Data will be transmitted ACK bit will be received 1 Load DAT from Slave Transmit buffer with first data byte 2 Write 0x04 to CONSET to set the...

Page 1153: ...LR to clear the SI flag 4 Increment Slave Transmit buffer pointer 5 Exit 43 11 9 4 State 0xC0 Data has been transmitted NOT ACK has been received Not addressed Slave mode is entered 1 Write 0x04 to CO...

Page 1154: ...C1_0 PC_3 yes yes ADC1_1 PC_0 yes yes yes ADC1_2 PF_9 yes yes ADC1_3 PF_6 yes yes ADC1_4 PF_5 yes yes ADC1_5 PF_11 yes yes ADC1_6 P7_7 yes yes yes yes ADC1_7 PF_7 yes yes DAC P4_4 yes yes yes yes ADC...

Page 1155: ...triggers are connected through the GIMA see Table 148 to the timers or SCT outputs For the ADC0 and ADC1 inputs that are multiplexed with digital functions the pins need to be configured using the ENA...

Page 1156: ...pins to ADC0 The A D converter cell can measure the voltage on any of these input signals These pins are not shared with ADC1 ADC1_ 7 0 Input Analog inputs Inputs from multiplexed analog digital pins...

Page 1157: ...ains DONE and OVERRUN flags for all of the A D channels as well as the A D interrupt flag 0 Table 1014 Table 1008 Register overview ADC0 base address 0x400E 3000 Name Access Address offset Description...

Page 1158: ...tion Bit Symbol Value Description Reset value 7 0 SEL Selects which of the ADCn_ 7 0 inputs are to be sampled and converted Bit 0 selects ADCn_0 bit 1 selects pin ADCn_1 and bit 7 selects pin ADCn_7 I...

Page 1159: ...defined 26 24 START Controls the start of an A D conversion when the BURST bit is 0 0 0x0 No start this value should be used when clearing PDN to 0 0x1 Start now 0x2 Start conversion when the edge sel...

Page 1160: ...not desirable at the end of each conversion for some A D channels Table 1011 A D Global Data register GDR address 0x400E 3004 ADC0 and 0x400E 4004 ADC1 bit description Bit Symbol Description Reset val...

Page 1161: ...nterrupt when bit 1 is one completion of a conversion on A D channel 1 will generate an interrupt etc 0x00 8 ADGINTEN When 1 enables the global DONE flag in ADDR to generate an interrupt When 0 only t...

Page 1162: ...n interrupt must be read in order to clear the corresponding DONE flag 44 7 3 DMA control A DMA transfer request is generated from the ADC interrupt request line To generate a DMA transfer the same co...

Page 1163: ...1163 of 1269 NXP Semiconductors UM10503 Chapter 44 LPC43xx 10 bit ADC0 1 The DMA transfer size determines when a DMA interrupt is generated The transfer size can be set to the number of ADC channels...

Page 1164: ...e NVIC For connecting to the GPDMA use the DMAMUX register Table 46 in the CREG block and enable the GPDMA channel in the DMA Channel Configuration registers Section 19 6 20 45 3 Features 10 bit resol...

Page 1165: ...ence level VREF for the D A converter VSSA Ground Table 1017 Register overview DAC base address 0x400E 1000 Name Access Address offset Description Reset value Reference CR R W 0x000 DAC register Holds...

Page 1166: ...te Table 1019 D A Control register CTRL address 0x400E 1004 bit description Bit Symbol Value Description Reset value 0 INT_DMA_REQ DMA request 0 0 This bit is cleared on any write to the DAC CR regist...

Page 1167: ...buffer which shares its register address with the DAC CR register The DAC CR itself will be loaded from the pre buffer whenever the counter reaches zero and the DMA request is set At the same time the...

Page 1168: ...for parts with and without on chip flash On parts with on chip flash ISP communication uses USART0 or USART3 depending on the OTP bits and or boot pins see Section 5 3 On flashless parts ISP communic...

Page 1169: ...s entered after a power on reset the IRC and PLL1 are used to generate the core clock of 96 MHz Pins P2_0 and P2_1 are used for communication with the USART0 and pins P2_3 and P2_4 are used for USART3...

Page 1170: ...of 1269 NXP Semiconductors UM10503 Chapter 46 LPC43xx flash programming ISP and IAP 46 4 2 Boot process for flashless parts See Figure 11 for the boot process flowchart for flashless parts If P2_7 is...

Page 1171: ...image see Section 46 4 4 1 and on parts with dual flash banks only one flash bank should contain a valid image You can use the ISP IAP command Set active boot flash bank to configure one flash bank wi...

Page 1172: ...d characters to verify synchronization If synchronization is verified then OK CR LF string is sent to the host The host should respond by sending 0 CR LF for backwards compatibility with existing tool...

Page 1173: ...ndler waits for a new command 46 4 5 6 Interrupts during IAP The on chip flash memory is not accessible during erase write operations When the user application code starts executing the interrupt vect...

Page 1174: ...8 0x1A00 6000 0x1A00 7FFF yes yes yes yes A 4 8 0x1A00 8000 0x1A00 9FFF yes yes yes yes A 5 8 0x1A00 A000 0x1A00 BFFF yes yes yes yes A 6 8 0x1A00 C000 0x1A00 DFFF yes yes yes yes A 7 8 0x1A00 E000 0x...

Page 1175: ...llowing ISP commands and restrictions Read Memory command disabled Copy RAM to Flash command cannot write to Sector 0 Go command disabled Erase sectors command can erase any individual sector except s...

Page 1176: ...ed or restricted ISP command will be terminated with return code CODE_READ_PROTECTION_ENABLED Table 1024 Code Read Protection hardware software interaction CRP option User Code Valid P2_7 pin at reset...

Page 1177: ...ble 1026 Set Baud Rate B Baud Rate stop bit yes yes Table 1027 Echo A setting yes yes Table 1028 Write to RAM W start address number of bytes yes yes Table 1029 Read Memory R address number of bytes y...

Page 1178: ...f the check sum matches the ISP command handler responds with OK CR LF to continue further transmission If the check sum does not match the ISP command handler responds with RESEND CR LF In response t...

Page 1179: ...tion 0x1C00 0000 and from the internal flash Table 1029 ISP Write to RAM command Command W Input Start Address RAM address where data bytes are to be written This address should be a word boundary Num...

Page 1180: ...tion command Command P Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Flash bank Selects flash bank if the part supports more than on bank 0 flash b...

Page 1181: ...ritten Should be 512 1024 4096 Return Code CMD_SUCCESS SRC_ADDR_ERROR Address not on word boundary DST_ADDR_ERROR Address not on correct boundary SRC_ADDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR By...

Page 1182: ...ENABLED Description This command is used to execute a program residing in RAM or flash memory It may not be possible to return to the ISP command handler once this command is successfully executed Thi...

Page 1183: ...Part Identification command Command J Input None Return Code CMD_SUCCESS followed by part identification number in ASCII see Table 1037 LPC43xx part identification numbers The command returns two wor...

Page 1184: ...mand K Input None Return Code CMD_SUCCESS followed by 2 bytes of boot code version number in ASCII format It is to be interpreted as byte1 Major byte0 Minor Description This command is used to read th...

Page 1185: ...not be accessible to update the flash Return Code CMD_SUCCESS Source and destination data are equal COMPARE_ERROR Followed by the offset of first mismatch COUNT_ERROR Byte count is not a multiple of 4...

Page 1186: ...e IAP command The maximum number of parameters is 4 passed to the Copy RAM to Flash command The maximum number of results is 4 returned by the Read device serial number command The command handler sen...

Page 1187: ...n it might create problems due to difference in the C compiler implementation from different vendors The suggested parameter passing scheme reduces this risk The flash memory is not accessible during...

Page 1188: ...operations Stack usage 88 B Table 1043 IAP Initialization command Command Init IAP Table 1044 IAP Prepare sectors for write operation command Command Prepare sectors for write operation Input Command...

Page 1189: ...DDR_NOT_MAPPED DST_ADDR_NOT_MAPPED COUNT_ERROR Byte count is not 512 1024 4096 SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION BUSY Result None Description This command is used to program the flash memory The...

Page 1190: ...TOR_NOT_BLANK Result1 Contents of non blank word location Description This command is used to blank check a sector or multiple sectors of on chip flash memory To blank check a single sector use the sa...

Page 1191: ...ird 32 bit word of Device Identification Number Result3 Fourth 32 bit word of Device Identification Number Description This command is used to read the device identification number The serial number m...

Page 1192: ...mmand ensure that the flash image content is executing as expected Otherwise the part may fail to boot after reset and for CRP level 3 external boot or ISP may not be accessible to update the flash Re...

Page 1193: ...host has been completely and successfully executed 0x0000 0001 INVALID_COMMAND Invalid command 0x0000 0002 SRC_ADDR_ERROR Source address is not on word boundary 0x0000 0003 DST_ADDR_ERROR Destination...

Page 1194: ...M can be executed during signature generation This can include interrupt services if the interrupt vector table is re mapped to memory other than the flash memory The code that initiates signature gen...

Page 1195: ...registers FMSW0 FMSW1 FMSW2 and FMSW3 The generated flash signature can be used to verify the flash memory contents The generated signature can be compared with an expected signature and thus makes s...

Page 1196: ...1 0 SW2 95 64 Word 2 of 128 bit signature bits 95 to 64 Table 1062 FMSW3 register bit description FMSW3 address 0x4000 C038 flash A and 0x4000 D038 flash B Bit Symbol Description Reset Value 31 0 SW3...

Page 1197: ...e flash A safe estimation for the duration of the signature generation is Duration int 60 tcy 3 x FMSSTOP FMSSTART 1 When signature generation is triggered via software the duration is in AHB clock cy...

Page 1198: ...ram time Endurance of 100k erase program cycles 47 4 General description The EEPROM can be read and written erased A write operation involves two steps The first step is writing a minimum of 1 word 4...

Page 1199: ...0 Table 1067 RWSTATE R W 0x008 EEPROM read wait state register 0x0000 0905 Table 1068 AUTOPROG R W 0x00C EEPROM auto programming register 0 Table 1069 WSTATE R W 0x010 EEPROM wait state register 0x00...

Page 1200: ...priate values in this wait state register for EEPROM operation The fields are 1 encoded so programming zero will result in a one cycle wait state The register contains two fields each representing a m...

Page 1201: ...he delays for the write and erase program operations are combined to simplify the software interface Timing for write and erase program operations is almost identical Table 1069 EEPROM auto programmin...

Page 1202: ...e of the frequency is 1500 kHz the lower limit is 800 kHz the maximum limit is 1600 kHz This clock is generated by dividing the system bus clock The clock divider register contains the division factor...

Page 1203: ...ter to put the EEPROM device in power down mode Do not put the EEPROM in power down mode during a pending EEPROM operation After clearing this bit any EEPROM operation has to be suspended for 100 s wh...

Page 1204: ...is undefined only zero should be written NA Table 1074 Interrupt enable set register INTENSET address 0x4000 EFDC bit description Bits Symbol Description Reset value 1 0 Reserved Read value is undefi...

Page 1205: ...ng bit of the INTENCLR register 0 31 3 Reserved The value read from a reserved bit is not defined NA Table 1077 Interrupt status clear register INTSTATCLR address 0x4000 EFE8 bit description Bits Symb...

Page 1206: ...ns at EEPROM_START 256 etc Writes to a page cannot cross a 128 page boundary Remark Before reading this data from the EEPROM or writing to another page program the contents of the page register into t...

Page 1207: ...th 1111100 automatically starts the erase program cycle This mode is useful to store multiple full pages of data During programming the EEPROM is not available for other operations To prevent undesire...

Page 1208: ...target resources are required for the debugging session Trace port provides CPU instruction trace capability Output can be via a 4 bit trace data port or Serial Wire Viewer Eight Breakpoints Six instr...

Page 1209: ...t The TMS pin selects the next state in the TAP state machine TDI Input JTAG Test Data In This is the serial data input for the shift register TDO Output JTAG Test Data Output This is the serial data...

Page 1210: ...nector 20 pin Figure 178 shows a standard JTAG connector The ARM Standard JTAG Connector provides support for Serial Wire and JTAG interface modes in a 20 pin 0 1 connector It can be used to access al...

Page 1211: ...ill be used there is also a debug with trace connector specification as shown in Figure 180 This small 20 pin 0 05 connector provides access to SWD SWV JTAG and ETM 4 bit signals Fig 179 Cortex Debug...

Page 1212: ...r is configured such that its clock rate is lower than the CPU clock rate the RIT may not increment predictably during some debug operations such as single stepping Debugging is disabled if code read...

Page 1213: ...nages to speculate the address early B The number of cycles required to perform the barrier operation For DSB and DMB the minimum number of cycles is zero For ISB the minimum number of cycles is equiv...

Page 1214: ...Rn Rm 2 to 12 1 Saturate Signed SSAT Rd imm op2 1 Unsigned USAT Rd imm op2 1 Compare Compare CMP Rn op2 1 Negative CMN Rn op2 1 Logical AND AND Rd Rn op2 1 Exclusive OR EOR Rd Rn op2 1 OR ORR Rd Rn o...

Page 1215: ...ng PC LDM Rn reglist PC 1 N P Store Word STR Rd Rn op2 2 2 Halfword STRH Rd Rn op2 2 2 Byte STRB Rd Rn op2 2 2 Signed halfword STRSH Rd Rn op2 2 2 Signed byte STRSB Rd Rn op2 2 2 User word STRT Rd Rn...

Page 1216: ...o CBNZ Rn label 1 or 1 P 3 Byte table branch TBB Rn Rm 2 P Halfword table branch TBH Rn Rm LSL 1 2 P State change Supervisor call SVC imm If then else IT cond 1 4 Disable interrupts CPSID flags 1 or 2...

Page 1217: ...multiply with 64 bit accumulate top by bottom SMLALTB 1 16 bit signed multiply with 64 bit accumulate top by top SMLALTT 1 16 bit signed multiply yielding 32 bit result bottom by bottom SMULBB 1 16 bi...

Page 1218: ...it to 16 bit signed addition SXTAB16 1 Extracted 16 bit to 32 bit signed addition SXTAH 1 Miscellaneous Data Processing Select bytes based on GE bits SEL 1 Unsigned sum of quad 8 bit unsigned absolute...

Page 1219: ...l 16 bit unsigned subtract USUB16 1 GE setting quad 8 bit unsigned subtract USUB8 1 Parallel Addition and Subtraction Dual 16 bit unsigned saturating addition and subtraction with exchange UQASX 1 Dua...

Page 1220: ...SP imm 1 From address from SP ADD Rd SP imm 1 From address from PC ADR Rd label 1 Subtract Lo and Lo SUBS Rd Rn Rm 1 3 bit immediate SUBS Rd Rn imm 1 8 bit immediate SUBS Rd Rd imm 1 With carry SBCS R...

Page 1221: ...Byte immediate offset STRB Rd Rn imm 2 Word register offset STR Rd Rn Rm 2 Halfword register offset STRH Rd Rn Rm 2 Byte register offset STRB Rd Rn Rm 2 SP relative STR Rd SP imm 2 Multiple STM Rn lo...

Page 1222: ...including PC and assumes load or store does not generate a HardFault exception 3 3 if taken 1 if not taken 4 Cycle count depends on core and debug configuration 5 Excludes time spend waiting for an i...

Page 1223: ...tion DAC Digital to Analog Converter DC DC Direct Current to Direct Current DMA Direct Memory Access GPIO General Purpose Input Output IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Ac...

Page 1224: ...NXP Semiconductors UM10503 Chapter 50 Supplementary information TTL Transistor Transistor Logic UART Universal Asynchronous Receiver Transmitter ULPI UTMI Low Pin Interface USART Universal Synchronou...

Page 1225: ...tors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of...

Page 1226: ...escription 69 Table 37 Event status register STATUS address 0x4004 4FE0 bit description 70 Table 38 Event enable register ENABLE address 0x4004 4FE4 bit description 71 Table 39 Clear event status regi...

Page 1227: ...SE_PERIPH_CLK control register BASE_PERIPH_CLK address 0x4005 0064 bit description 119 Table 87 BASE_USB1_CLK control register BASE_USB1_CLK address 0x4005 0068 bit description 120 Table 88 BASE_M4_CL...

Page 1228: ...sters for normal drive pins SFS address 0x4008 6000 SPSP0_0 to 0x4008 67AC SFSPF_11 bit description 292 Table 134 Pin configuration registers for high drive pins SFS address 0x4008 60C4 SFSP1_17 to 0x...

Page 1229: ...ress 0x400C 706C bit description 326 Table 178 ADC start0 input multiplexer ADCSTART0_IN address 0x400C 7070 bit description 327 Table 179 ADC start1 input multiplexer ADCSTART1_IN address 0x400C 7074...

Page 1230: ...ter registers COUNT0 to 15 addresses 0x4010 1180 to 0x4010 11BC bit description 359 Table 222 Position registers POS0 to 15 addresses 0x4010 11C0 to 0x4010 11FC bit description 360 Table 223 Slice A m...

Page 1231: ...able 271 Register overview GPDMA base address 0x4000 2000 386 Table 272 DMA Interrupt Status register INTSTAT address 0x4000 2000 bit description 388 Table 273 DMA Interrupt Terminal Count Request Sta...

Page 1232: ...x4000 4078 bit description 433 Table 323 Bus Mode Register BMOD address 0x4000 4080 bit description 434 Table 324 Poll Demand Register PLDMND address 0x4000 4084 bit description 434 Table 325 Descript...

Page 1233: ...TICWAITWEN 0 3 address 0x4000 5204 STATICWAITWEN0 0x4000 5224 STATICWAITWEN1 0x4000 5244 STATICWAITWEN2 0x4000 5264 STATICWAITWEN3 bit description 488 Table 377 Static Memory Output Enable delay regis...

Page 1234: ...it description 536 Table 423 USB Mode register in device mode USBMODE_D address 0x4000 61A8 bit description 538 Table 424 USB Mode register in host mode USBMODE_H address 0x4000 61A8 bit description 5...

Page 1235: ...Endpoint NAK Enable register in device mode ENDPTNAKEN address 0x4000 717C bit description 611 Table 481 Port Status and Control register in device mode PORTSC1_D address 0x4000 7184 bit description...

Page 1236: ...MAC Interrupt status register MAC_INTR address 0x4001 0038 bit description 695 Table 545 MAC Interrupt mask register MAC_INTR_MASK address 0x4001 003C bit description 696 Table 546 MAC Address 0 high...

Page 1237: ...s 0x4000 8000 768 Table 603 Horizontal Timing register TIMH address 0x4000 8000 bit description 770 Table 604 Vertical Timing register TIMV address 0x4000 8004 bit description 771 Table 605 Clock and...

Page 1238: ...ster EVEN address 0x4000 00F0 bit description 829 Table 663 SCT event flag register EVFLAG address 0x4000 00F4 bit description 829 Table 664 SCT conflict enable register CONEN address 0x4000 00F8 bit...

Page 1239: ...iption 872 Table 705 MCPWM Timer Counter 0 to 2 registers TC 0x400A 0018 TC0 0x400A 001C TC1 0x400A 0020 TC2 bit description 873 Table 706 MCPWM Limit 0 to 2 registers LIM 0x400A 0024 LIM0 0x400A 0028...

Page 1240: ...ption 913 Table 761 Alarm timer clocking and power control 915 Table 762 Register overview Alarm timer base address 0x4004 0000 916 Table 763 Downcounter register DOWNCOUNTER 0x4004 0000 bit descripti...

Page 1241: ...819 USART0 2 3 clocking and power control 948 Table 820 USART0 2 3 pin description 951 Table 821 Register overview USART0 2 3 base address 0x4008 1000 0x400C 1000 0x400C 2000 951 Table 822 USART Rece...

Page 1242: ...859 UART1 Line Status Register LSR address 0x4008 2014 bit description 993 Table 860 UART1 Modem Status Register MSR address 0x4008 2018 bit description 995 Table 861 UART1 Scratch Pad Register SCR a...

Page 1243: ...dress 0x400A 202C I2S0 and 0x400A 302C I2S1 bit description 1041 Table 910 I2S Transmit Mode Control register TXMODE address 0x400A 2030 I2S0 and 0x400A 3030 I2S1 bit description 1041 Table 911 I2S Re...

Page 1244: ...0x400A 4038 C_CAN1 bit description 1084 Table 957 CAN message interface message control registers IF2_MCTRL address 0x400E 2098 C_CAN0 and 0x400A 4098 C_CAN1 bit description 1086 Table 958 CAN messag...

Page 1245: ...le 1002 Slave Receiver mode 1137 Table 1003 Slave Transmitter mode 1141 Table 1004 Miscellaneous States 1143 Table 1005 ADC channels for different packages 1154 Table 1006 ADC0 1 clocking and power co...

Page 1246: ...h module Status register FMSTAT address 0x4000 CFE0 flash A and 0x4000 DFE0 flash B bit description 1196 Table 1064 Flash Module Status Clear register FMSTATCLR address 0x4000 CFE8 flash A and 0x4000...

Page 1247: ...ck diagram 415 Fig 46 Dual buffer descriptor structure 459 Fig 47 Chain descriptor structure 460 Fig 48 EMC block diagram SDRAM 468 Fig 49 EMC block diagram SRAM 469 Fig 50 32 bit bank external memory...

Page 1248: ...g and pin connections 1044 Fig 135 Typical transmitter master mode PCLK no MCLK output 1045 Fig 136 Transmitter master mode PCLK with MCLK output 1046 Fig 137 Transmitter master mode sharing RX_MCLK 1...

Page 1249: ...on Unit MPU 20 3 4 Memory map flashless parts 21 3 5 Memory map parts with on chip flash 23 3 6 AHB Multilayer matrix configuration 26 Chapter 4 LPC43xx One Time Programmable OTP memory and API 4 1 Ho...

Page 1250: ...st register 87 9 4 14 USB1 frame length adjust register 87 Chapter 10 LPC43xx Power Management Controller PMC 10 1 How to read this chapter 89 10 2 General description 89 10 2 1 Active mode 89 10 2 2...

Page 1251: ...mode 132 Non integer mode 133 Direct mode 133 Power down mode 133 11 8 Example CGU configurations 134 11 8 1 Programming the CGU for Deep sleep and Power down modes 134 11 8 2 Programming the CGU for...

Page 1252: ...CAP0_3 capture input multiplexer CAP0_3_IN 312 16 4 5 Timer 1 CAP1_0 capture input multiplexer CAP1_0_IN 312 16 4 6 Timer 1 CAP1_1 capture input multiplexer CAP1_1_IN 313 16 4 7 Timer 1 CAP1_2 capture...

Page 1253: ...practices 347 Chapter 18 LPC43xx Serial GPIO SGPIO 18 1 How to read this chapter 348 18 2 Basic configuration 348 18 3 Features 348 18 4 General description 349 18 4 1 Interrupts 350 18 5 Pin descrip...

Page 1254: ...quest Register 391 19 6 10 DMA Software Single Request Register 391 19 6 11 DMA Software Last Burst Request Register 392 19 6 12 DMA Software Last Single Request Register 392 19 6 13 DMA Configuration...

Page 1255: ...onal description 437 20 7 1 Power pull up control and card detection unit 437 20 7 2 Auto Stop 438 20 7 3 Software hardware restrictions 439 20 7 4 Programming sequence 441 20 7 4 1 Initialization 441...

Page 1256: ...uffers 493 21 8 4 1 Write buffers 493 21 8 4 2 Read buffers 493 21 8 5 Using the EMC with SDRAM 494 21 8 5 1 SDRAM burst length 494 21 8 5 2 SDRAM mode register burst length set up 494 21 8 5 2 1 Exam...

Page 1257: ...6 Split state machines 552 23 8 1 7 Asynchronous Transaction scheduling and buffer management 552 23 8 1 8 Periodic Transaction scheduling and buffer management 552 23 8 1 9 Multiple Transaction Tran...

Page 1258: ...ss DEVICEADDR and Periodic List Base PERIODICLISTBASE registers 604 24 6 6 1 Device mode 604 24 6 6 2 Host mode 604 24 6 7 Endpoint List Address register ENDPOINTLISTADDR and Asynchronous List Address...

Page 1259: ...ent register 699 26 6 18 System time seconds register 700 26 6 19 System time nanoseconds register 700 26 6 20 System time seconds update register 701 26 6 21 System time nanoseconds update register 7...

Page 1260: ...7 6 3 Clock and Signal Polarity register 771 27 6 4 Line End Control register 773 27 6 5 Upper Panel Frame Base Address register 774 27 6 6 Lower Panel Frame Base Address register 774 27 6 7 LCD Contr...

Page 1261: ...Configure events and event responses 841 28 7 10 1 4 Configure multiple states 842 28 7 10 1 5 Miscellaneous options 842 28 7 10 2 Operate the SCT 842 28 7 10 3 Configure the SCT without using states...

Page 1262: ...x Compare register 0 901 31 6 2 8 QEI Timer Reload register 901 31 6 2 9 QEI Timer register 901 31 6 2 10 QEI Velocity register 901 31 6 2 11 QEI Velocity Capture register 902 31 6 2 12 QEI Velocity C...

Page 1263: ...939 36 4 Applications 939 36 5 General description 940 36 6 Pin description 942 36 7 Register description 942 36 7 1 Event Monitor Recorder Control Register 943 36 7 2 Event Monitor Recorder Status R...

Page 1264: ...9 38 7 Functional description 999 38 7 1 Auto flow control 999 38 7 1 1 Auto RTS 999 38 7 1 2 Auto CTS 1000 38 7 2 Auto baud 1001 38 7 3 Auto baud modes 1001 38 7 4 Baud rate calculation 1001 38 7 5 R...

Page 1265: ...K with MCLK output 1053 41 7 2 2 3 Receiver master mode sharing TX_MCLK 1054 41 7 2 2 4 Typical Receiver slave mode 1055 41 7 2 2 5 4 Wire Receiver mode 1056 41 7 2 2 6 Receiver master mode PLLAUDIO 1...

Page 1266: ...he appropriate I2C data rate and duty cycle 1116 43 7 6 I2C Control Clear register 1117 43 7 7 I2C Monitor mode control register 1117 43 7 7 1 Interrupt in Monitor mode 1118 43 7 7 2 Loss of arbitrati...

Page 1267: ...control 1162 Chapter 45 LPC43xx DAC 45 1 How to read this chapter 1164 45 2 Basic configuration 1164 45 3 Features 1164 45 4 Pin description 1164 45 5 Register description 1165 45 5 1 D A converter re...

Page 1268: ...register 1196 46 11 1 4 Flash Module Status Clear register 1196 46 11 2 Algorithm and procedure for signature generation 1197 Signature generation 1197 Content verification 1197 Chapter 47 LPC43xx EEP...

Page 1269: ...Date of release 6 July 2012 Document identifier UM10503 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal informati...

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