UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
501 of 1269
NXP Semiconductors
UM10503
Chapter 22: LPC43xx SPI Flash Interface (SPIFI)
Serial flash devices respond to commands sent by software or automatically sent by the
SPIFI when software reads either of the two read-only serial flash regions in the memory
map (see
).
22.5 Pin description
22.6 Supported QSPI devices
Table 224 shows a list of vendor QSPI devices which are verified to support the SPIFI API.
Other devices can be used and will run in basic single SPI mode at lower speed.
Remark:
All QSPI devices have been tested at an operating voltage of 3.3 V.
Table 384. SPIFI flash memory map
Memory
Address
SPIFI data
0x1400 0000 to 0x17FF FFFF (Use this memory area for debugging code).
0x8000 0000 to 0x87FF FFFF (Debug will not work if the program counter is in this
memory area).
Remark:
These are the spaces allocated to the SPIFI in the LPC43xx. The same
data appears in the first area and the first half of the second area. These areas
allow maxima of 64 MB and 128 MB of SPI flash to be mapped into the Cortex-M4
memory space. In practice, the usable space is limited to the size of the connected
device.
Table 385. SPIFI Pin description
Pin function
Direction
Description
SPIFI_SCK
O
Serial clock for the flash memory, switched only during active bits on the MOSI/IO0,
MISO/IO1, and IO3:2 lines.
SPIFI_CS
O
Chip select for the flash memory, driven low while a command is in progress, and high
between commands. In the typical case of one serial slave, this signal can be
connected directly to the device. If more than one serial slave is connected, software
and off-chip hardware should use general-purpose I/O signals in combination with this
signal to generate the chip selects for the various slaves.
SPIFI_MOSI or IO0
I/O
This is an output except in quad/dual input data fields. After a quad/dual input data
field, it becomes an output again one serial clock period after CS goes high.
SPIFI_MISO or IO1
I/O
This is an output in quad/dual opcode, address, intermediate, and output data fields,
and an input in SPI mode and in quad/dual input data fields. After an input data field in
quad/dual mode, it becomes an output again one serial clock period after CS goes
high.
SPIFI_SIO[3:2]
I/O
These are outputs in quad opcode, address, intermediate, and output data fields, and
inputs in quad input data fields. If the flash memory does not have quad capability,
these pins can be assigned to GPIO or other functions.
