NXP Semiconductors LCP43 Series, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 283 of 1269
NXP Semiconductors
UM10503
Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration
15.3.3 Input buffer
To be able to receive a digital signal, the input buffer must be enabled through bit EZI in
the pin configuration registers (see
Figure 32 ). By default, the input buffer is disabled.
For pads that support both a digital and an analog function, the input buffer must be
disabled before enabling the analog function (see
Section 15.4.6 to Section 15.4.8 ).
15.3.4 Programmable glitch filter
All digital pins support a programmable glitch filter (bit ZIF), which can be switched on or
off (see
Figure 32 ). By default, the glitch filter is on. The glitch filter should be disabled for
clocking signals with frequencies higher than 30 MHz.
15.3.5 Programmable slew rate
Normal-drive and high-speed pins support a programmable slew rate (bit EHS) to select
between lower noise and speed or higher noise and speed (see
Figure 32 ). The typical
frequencies supported are 50 MHz/80 MHz for normal-drive pins and 75 MHz/204 MHz for
high-speed pins.
15.3.6 High-speed pins
The clock pins CLK0 to CLK3 and P3_3 support a programmable high-speed output with
typical frequencies of 75 MHz or 204 MHz depending on the slew rate setting (see
Section 15.3.5 ).
15.3.7 High-drive pins
Selected pins (see Section 15.4.2 ) support a high-drive output with four programmable
levels.
High-drive pins support the programmable glitch filter but not the programmable slew rate.
15.3.8 I
2
C0-bus pins
The SFSI2C0 register ( Table 137 ) allows to configure different modes for I
2
C0-bus
interface:
•
Standard mode/Fast-mode I
2
C with an open-drain output according to the I
2
C-bus
specification. This is the default mode.
•
Fast-mode Plus mode with an open-drain output according to the I
2
C-bus
specification.
The I2C0 pins use a programmable glitch filter (bit ZIF).
Remark: The input buffer must be enabled for the I2C0 pins SDA and SCL for proper
operation.
15.3.9 USB1 USB1_DP/USB1_DM pins
The input signal to the USB1 is controlled by the SFSUSB register ( Table 136 ). The
USB_ESEA bit in this register must be set to one to enable the USB1 block.