NXP Semiconductors LCP43 Series, User Manual

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User manual Rev. 1.3 — 6 July 2012 161 of 1269
NXP Semiconductors
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Chapter 13: LPC43xx Reset Generation Unit (RGU)
8 ADC0_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
9 ADC1_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
10 DAC_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
11 - Reserved - -
12 UART0_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
13 UART1_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
14 UART2_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
15 UART3_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
16 I2C0_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
17 I2C1_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
18 SSP0_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
19 SSP1_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
20 I2S_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
21 SPIFI_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
22 CAN1_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
23 CAN0_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
24 M0APP_RST Writing a one activates the reset. Writing a 0 clears the reset.
This bit must be cleared by software.
1 W
25 SGPIO_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
26 SPI_RST Writing a one activates the reset. This bit is automatically
cleared to 0 after one clock cycle. 0 W
27 - Reserved - -
28 - Reserved - -
29 - Reserved - -
30 - Reserved - -
31 - Reserved - -
Table 115. Reset control register 1 (RESET_CTRL1, address 0x4005 3104) bit description
…continued
Bit Symbol Description Reset
value Access