NXP Semiconductors LCP43 Series, User Manual

Page: 197 / 1269

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 197 of 1269
NXP Semiconductors
UM10503
Chapter 14: LPC43xx Pin configuration
P6_3 P15 N13 - 113 79
[3]
N;
PU I/O GPIO3[2] — General purpose digital input/output pin.
O USB0_PPWR — VBUS drive signal (towards external
charge pump or power management unit); indicates that
the VBUS signal must be driven (active HIGH).
Add a pull-down resistor to disable the power switch at
reset. This signal has opposite polarity compared to the
USB_PPWR used on other NXP LPC parts.
I/O SGPIO4 — General purpose digital input/output pin.
O EMC_CS1 — LOW active Chip Select 1 signal.
- R — Function reserved.
I T2_CAP2 — Capture input 2 of timer 2.
- R — Function reserved.
- R — Function reserved.
P6_4 R16 M14 F6 114 80
[3]
N;
PU I/O GPIO3[3] — General purpose digital input/output pin.
I CTIN_6 — SCT input 6. Capture input 1 of timer 3.
O U0_TXD — Transmitter output for USART0.
O EMC_CAS — LOW active SDRAM Column Address
Strobe.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
P6_5 P16 L14 F9 117 82
[3]
N;
PU I/O GPIO3[4] — General purpose digital input/output pin.
O CTOUT_6 — SCT output 6. Match output 2 of timer 1.
I U0_RXD — Receiver input for USART0.
O EMC_RAS — LOW active SDRAM Row Address Strobe.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
- R — Function reserved.
Table 129. Pin description
…continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts.
Symbol
LB
GA25
6
TFBGA180 TFBGA100 LQ
FP2
08
[1
]
LQ
FP1
44
R
e
se
t st
ate
[2
]
Ty
p
e
Description