UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
440 of 1269
NXP Semiconductors
UM10503
Chapter 20: LPC43xx SD/MMC interface
Before issuing a new data transfer command, the software should ensure that the card is
not busy due to any previous data transfer command. Before changing the card clock
frequency, the software must ensure that there are no data or command transfers in
progress.
To avoid glitches in the card clock outputs (cclk_out), the software should use the
following steps when changing the card clock frequency:
1. Update the Clock Enable register to disable all clocks. To ensure completion of any
previous command before this update, send a command to the CIU to update the
clock registers by setting:
–
start_cmd bit
–
"update clock registers only" bits
–
"wait_previous data complete" bit
Wait for the CIU to take the command by polling for 0 on the start_cmd bit.
2. Set the start_cmd bit to update the Clock Divider and/or Clock Source registers, and
send a command to the CIU in order to update the clock registers; wait for the CIU to
take the command.
3. Set start_cmd to update the Clock Enable register in order to enable the required
clocks and send a command to the CIU to update the clock registers; wait for the CIU
to take the command.
In non-DMA mode, while reading from a card, the Data Transfer Over (RINTSTS[3])
interrupt occurs as soon as the data transfer from the card is over. There still could be
some data left in the FIFO, and the RX_WMark interrupt may or may not occur, depending
on the remaining bytes in the FIFO. Software should read any remaining bytes upon
seeing the Data Transfer Over (DTO) interrupt. In DMA mode while reading from a card,
the DTO interrupt occurs only after all the FIFO data is flushed to memory by the DMA
Interface unit.
While writing to a card in DMA mode, if an undefined-length transfer is selected by setting
the Byte Count register to 0, the DMA logic will likely request more data than it will send to
the card, since it has no way of knowing at which point the software will stop the transfer.
The DMA request stops as soon as the DTO is set by the CIU.
If the software issues a controller_reset command by setting control register bit[0] to 1, all
the CIU state machines are reset; the FIFO is not cleared. The DMA sends all remaining
bytes to the cpu. In addition to a card-reset, if a FIFO reset is also issued, then:
•
Any pending DMA transfer on the bus completes correctly
•
DMA data read is ignored
•
Write data is unknown (x)
Additionally, if dma_reset is also issued, any pending DMA transfer is abruptly terminated.
The DMA controller channel should also be reset and reprogrammed.
If any of the previous data commands do not properly terminate, then the software should
issue the FIFO reset in order to remove any residual data, if any, in the FIFO. After
asserting the FIFO reset, you should wait until this bit is cleared.
