UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
800 of 1269
NXP Semiconductors
UM10503
Chapter 27: LPC43xx LCD
1. When power is applied, the following signals are held LOW:
•
LCDLP
•
LCDDCLK
•
LCDFP
•
LCDENAB/ LCDM
•
LCDVD[23:0]
•
LCDLE
2. When LCD power is stabilized, a 1 is written to the LcdEn bit in the CTRL register. This
enables the following signals into their active states:
•
LCDLP
•
LCDDCLK
•
LCDFP
•
LCDENAB/ LCDM
•
LCDLE
The LCDV[23:0] signals remain in an inactive state.
3. When the signals in step 2 have stabilized, the contrast voltage (not controlled or
supplied by the LCD controller) is applied to the LCD panel.
4. If required, a software or hardware timer can be used to provide the minimum display
specific delay time between application of the control signals and power to the panel
display. On completion of the time interval, power is applied to the panel by writing a 1 to
the LcdPwr bit within the CTRL register that, in turn, sets the LCDPWR signal high and
enables the LCDV[23:0] signals into their active states. The LCDPWR signal is intended
to be used to gate the power to the LCD panel.
The power-down sequence is the reverse of the above four steps and must be strictly
followed, this time, writing the respective register bits with 0.
shows the power-up and power-down sequences.
