NXP Semiconductors LCP43 Series, User Manual

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User manual Rev. 1.3 — 6 July 2012 627 of 1269
NXP Semiconductors
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Chapter 24: LPC43xx USB1 Host/Device controller
[1] For control endpoints only: There is a slight delay (50 clocks max) between the ENPTSETUPSTAT being cleared and hardware
continuing to clear this bit. In most systems it is unlikely that the DCD software will observe this delay. However, should the DCD notice
that the stall bit is not set after writing a one to it, software should continually write this stall bit until it is set or until a new setup has been
received by checking the associated ENDPTSETUPSTAT bit.
24.7 Functional description
For details on the device data structures, see Section 23.9 . For the device operational
model, see Section 23.10 .
24.7.1 Susp_CTRL module
The SUSP_CTRL module implements the power management logic of USB block. It
controls the suspend input of the transceiver. Asserting this suspend signal
(PORTSC1.PHCD bit)
will put the transceiver in suspend mode and the 60 MHz clock will
be switched off.
In suspend mode, the transceiver will raise an output signal.
For USB1, this signal is not
connected to any register.
The SUSP_CTRL module also generates an output signal indicating whether the AHB
clock is needed or not. If not, the AHB clock is allowed to be switched off or reduced in
frequency in order to save power.
For USB1, this signal is connected to event #10 (USB1_L) in the event router (see
Table 22
). Software should check for this signal to be low before stopping the USB PLL
and putting the chip in low power mode. Note that the event router block doesn't have a
21 TXI Tx data toggle inhibit
This bit is only used for test and should always be written as zero.
Writing a one to this bit will cause this endpoint to ignore the data
toggle sequence and always accept data packets regardless of their
data PID.
0 R/W
0 Enabled
1 Disabled
22 TXR Tx data toggle reset
Write 1 to reset the PID sequence.
Whenever a configuration event is received for this Endpoint,
software must write a one to this bit in order to synchronize the data
PID’s between the host and device.
1 WS
23 TXE Tx endpoint enable
Remark: An endpoint should be enabled only after it has been
configured
0 R/W
0 Endpoint disabled.
1 Endpoint enabled.
31:24 - - Reserved 0
Table 492. USB Endpoint 1 to 3 control registers (ENDPTCTRL - address 0x4000 71C4 (ENDPTCTRL1) to
0x4000 71CC (ENDPTCTRL3)) bit description
…continued
Bit Symbol Value Description Reset
value Access