UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
282 of 1269
NXP Semiconductors
UM10503
Chapter 15: LPC43xx System Control Unit (SCU)/ IO configuration
15.3.1 Digital pin function
The FUNC bits in the SFS registers control the function of each pin. Each pin can support
up to eight digital functions.Some pins support an additional analog function. If the
function is GPIO, the DIR registers determine whether the pin is configured as an input or
output (see
). For any peripheral function, the pin direction is controlled
automatically depending on the pin’s functionality. The GPIO DIR registers do not affect
peripheral functions.
15.3.2 Digital pin mode
) in the SFS registers allow the selection of weak
on-chip pull-up or pull-down resistors with a typical value of 50 k
for each pin or the
selection of the repeater mode.
The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
pull-up/pull-down. The default value is pull-up enabled.
The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
known state if it is configured as an input and is not driven externally. Repeater mode may
typically be used to prevent a pin from floating (and potentially using significant power if it
floats to an indeterminate state) if it is temporarily not driven.
To select the repeater mode, enable both the pull-up and the pull-down resistor in the SFS
registers.
Fig 32. Block diagram of the I/O pad
slew rate bit EHS
pull-up enable bit EPUN
pull-down enable bit EPD
glitch
filter
analog I/O
ESD
ESD
PIN
VDDIO
VSSIO
input buffer enable bit EZI
filter select bit ZIF
data input to core
data output from core
enable output driver
