UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
739 of 1269
NXP Semiconductors
UM10503
Chapter 26: LPC43xx Ethernet
The Transmit and Receive engines enter the Running state and attempt to acquire
descriptors from the respective descriptor lists. The Receive and Transmit engines then
begin processing Receive and Transmit operations. The Transmit and Receive processes
are independent of each other and can be started or stopped separately.
26.7.5.1.1
Host bus burst access
The DMA attempts to execute fixed-length Burst transfers on the AHB Master interface if
configured to do so (FB bit of DMA Register 0). The maximum Burst length is indicated
and limited by the PBL field (DMA Register 0[13:8]). The Receive and Transmit
descriptors are always accessed in the maximum possible (limited by PBL or 16 x 8/bus
width) burst-size for the 16-bytes to be read.
The Transmit DMA initiates a data transfer only when sufficient space to accommodate
the configured burst is available in MTL Transmit FIFO or the number of bytes till the end
of frame (when it is less than the configured burst-length). The DMA indicates the start
address and the number of transfers required to the AHB Master Interface. When the AHB
Interface is configured for fixed-length burst, then it transfers data using the best
combination of INCR4/8/16 and SINGLE transactions. Otherwise (no fixed-length burst), it
transfers data using INCR (undefined length) and SINGLE transactions.
The Receive DMA initiates a data transfer only when sufficient data to accommodate the
configured burst is available in MTL Receive FIFO or when the end of frame (when it is
less than the configured burst-length) is detected in the Receive FIFO. The DMA indicates
the start address and the number of transfers required to the AHB Master Interface. When
the AHB Interface is configured for fixed-length burst, then it transfers data using the best
combination of INCR4/8/16 and SINGLE transactions. If the end-of frame is reached
before the fixed-burst ends on the AHB interface, then dummy transfers are performed in
order to complete the fixed-burst. Otherwise (FB bit of DMA Register
is reset), it
transfers data using INCR (undefined length) and SINGLE transactions.
When the AHB interface is configured for address-aligned beats, both DMA engines
ensure that the first burst transfer the AHB initiates is less than or equal to the size of the
configured PBL. Thus, all subsequent beats start at an address that is aligned to the
configured PBL. The DMA can only align the address for beats up to size 16 (for PBL >
16), because the AHB interface does not support more than INCR16.
26.7.5.1.2
Host data buffer alignment
The Transmit and Receive data buffers do not have any restrictions on start address
alignment. For example, in systems with 32-bit memory, the start address for the buffers
can be aligned to any of the four bytes. However, the DMA always initiates transfers with
address aligned to the bus width with dummy data for the byte lanes not required. This
typically happens during the transfer of the beginning or end of an Ethernet frame.
Example: Buffer read
If the Transmit buffer address is 0x00000FF2 (for 32-bit data bus), and 15 bytes need to
be transferred, then the DMA reads five full words from address 0x00000FF0, but when
transferring data to the MTL Transmit FIFO, the extra bytes (the first two bytes) are
dropped or ignored. Similarly, the last 3 bytes of the last transfer are also ignored. The
DMA always ensures it transfers a full 32-bit data to the MTL Transmit FIFO, unless it is
the end-of-frame.
