NXP Semiconductors LCP43 Series, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 42 of 1269
NXP Semiconductors
UM10503
Chapter 5: LPC43xx Boot ROM
5.3.5.3 SPI boot mode
The boot uses SSP0 in SPI mode. The SPI clock is 18 MHz.
Figure 15 details the boot-flow steps of the SPI flash boot mode. The execution of this
mode occurs only if the boot mode is set accordingly (see boot modes Table 18 and
Table 19 ).
5.3.5.4 SPIFI boot mode
Figure 16 details the boot-flow steps of the Quad SPI flash boot mode. The execution of
this mode occurs only if the boot mode is set accordingly (see boot modes in Table 18
and Table 19 ). The boot code sets the SPIFI clock to 18 MHz at the beginning of the boot
process and checks for the type of SPI flash device. For an SPI flash, the part boots with a
18 MHz clock. For a quad SPI flash device, the part boots with a 32 MHz clock. If the
detected device is unknown, the SPIFI clock is reduced to 18 MHz.
Fig 14. EMC boot process
Setup Pin
Configuration
EMC _A[13:0]
EMC_CS0
Read Image
Header
Image size
> 16384-16
Extend
address bus
yes
no
see main boot flow
Fig 15. SPI boot process
Setup Pin
Configuration
P3_3, P3_6..P3_8
see main boot flow
Setup clock
SSP0_SCK=
18MHz