NXP Semiconductors LCP43 Series, User Manual

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 1.3 — 6 July 2012 84 of 1269
NXP Semiconductors
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Chapter 9: LPC43xx Configuration Registers (CREG)
9.4.7 ETB SRAM configuration register
This register selects how the 16 kB block of RAM located at address 0x2000 C000 is
used. This RAM memory block can be accessed either by the ETB or be used as normal
SRAM on the AHB bus.
9.4.8 CREG6 control register
This register controls various aspects of the LPC43xx:
•
Bits 2:0 control the Ethernet PHY interface. The ethernet block reads this register
during set-up. Therefore the ethernet must be reset after changing the PHY interface.
Table 48. Flash Accelerator Configuration for flash bank B register (FLASHCFGB - address 0x4004 3124) bit
description
Bit Symbol Value Description Reset value
11:0 - - Reserved. Do not change these bits from the reset value. <tbd>
15:12 FLASHTIM Flash access time. The value of this field plus 1 gives the number of
BASE_M4_CLK clocks used for a flash access.
Warning: Improper setting of this value may result in incorrect operation of the
device.
All other values are reserved.
<tbd>
0x0 1 BASE_M4_CLK clock. Use for BASE_M4_CLK up to 21 MHz.
0x1 2 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 43 MHz.
0x2 3 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 64 MHz.
0x3 4 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 86 MHz.
0x4 5 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 107 MHz.
0x5 6 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 129 MHz.
0x6 7 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 150 MHz.
0x7 8 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 172 MHz.
0x8 9 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 193 MHz.
0x9 10 BASE_M4_CLK clocks. Use for BASE_M4_CLK up to 204 MHz. Safe setting
for all allowed conditions.
30:16 - Reserved. Read value is undefined. Write only zeros to these bits. <tbd>
31 POW Flash bank A power control 1
0 Power-down
1 Active (Default)
Table 49. ETB SRAM configuration register (ETBCFG, address 0x4004 3128) bit description
Bit Symbol Value Description Reset
value Access
0 ETB Select SRAM interface 1 R/W
0 ETB accesses SRAM at address 0x2000 C000.
1 AHB accesses SRAM at address 0x2000 C000.
31:1 - Reserved. - -