UM10503
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User manual
Rev. 1.3 — 6 July 2012
741 of 1269
NXP Semiconductors
UM10503
Chapter 26: LPC43xx Ethernet
26.7.5.2 Transmission
26.7.5.2.1
TxDMA operation: Default (non-OSF) mode
The transmit DMA engine in default mode proceeds as follows:
1. The Host sets up the transmit descriptor (TDES0-TDES3) and sets the Own bit
(TDES0[31]) after setting up the corresponding data buffer(s) with Ethernet Frame
data.
2. Once the ST bit (DMA Register) is set, the DMA enters the Run state.
3. While in the Run state, the DMA polls the Transmit Descriptor list for frames requiring
transmission. After polling starts, it continues in either sequential descriptor ring order
or chained order. If the DMA detects a descriptor flagged as owned by the Host, or if
an error condition occurs, transmission is suspended and both the Transmit Buffer
Unavailable (DMA Register
) and Normal Interrupt Summary (DMA Register
) bits are set. The Transmit Engine proceeds to Step 9.
4. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA
decodes the Transmit Data Buffer address from the acquired descriptor.
5. The DMA fetches the Transmit data from the Host memory and transfers the data to
the MTL for transmission.
6. If an Ethernet frame is stored over data buffers in multiple descriptors, the DMA
closes the intermediate descriptor and fetches the next descriptor. Steps 3, 4, and 5
are repeated until the end-of-Ethernet-frame data is transferred to the MTL.
7. When frame transmission is complete, if IEEE 1588 time stamping was enabled for
the frame (as indicated in the transmit status) the timestamp value obtained from MTL
is written to the transmit descriptor (TDES2 and TDES3) that contains the
end-of-frame buffer. The status information is then written to this transmit descriptor
(TDES0). Because the Own bit is cleared during this step, the Host now owns this
descriptor. If time stamping was not enabled for this frame, the DMA does not alter the
contents of TDES2 and TDES3.
8. Transmit Interrupt (DMA Register
) is set after completing transmission of a
frame that has Interrupt on Completion (TDES1[31]) set in its Last Descriptor. The
DMA engine then returns to Step 3.
9. In the Suspend state, the DMA tries to re-acquire the descriptor (and thereby return to
Step 3) when it receives a Transmit Poll demand and the Underflow Interrupt Status
bit is cleared.
The TxDMA transmission flow in default mode is shown in
.
