UM10503
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
5 of 1269
NXP Semiconductors
UM10503
Chapter 1: Introductory information
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Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
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64 kB ROM containing boot code and on-chip software drivers.
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32 bit general-purpose One-Time Programmable (OTP) memory.
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On-chip memory (parts with on-chip flash)
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Up to 1 MB on-chip dual bank flash memory with flash accelerator.
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16 kB on-chip EEPROM data memory.
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136 kB SRAM for code and data use.
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Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
–
64 kB ROM containing boot code and on-chip software drivers.
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128 bit general-purpose One-Time Programmable (OTP) memory.
•
Configurable digital peripherals
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Serial GPIO (SGPIO) interface.
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State Configurable Timer (SCT) subsystem on AHB.
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Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCT, and ADC0/1.
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Serial interfaces
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Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to 60 MB
per second.
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10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping and advanced
time stamping (IEEE 1588-2008 v2).
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One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
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One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
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USB interface electrical test software included in ROM USB stack.
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One 550 UART with DMA support and full modem interface.
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Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
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Two C_CAN 2.0B controllers with one channel each.
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Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
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One SPI controller.
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One Fast-mode Plus I
2
C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I
2
C-bus specification. Supports data rates of up to
1 Mbit/s.
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One standard I
2
C-bus interface with monitor mode and with standard I/O pins.
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Two I
2
S interfaces, each with DMA support and with one input and one output.
