UM10503
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© NXP B.V. 2012. All rights reserved.
User manual
Rev. 1.3 — 6 July 2012
514 of 1269
NXP Semiconductors
UM10503
Chapter 23: LPC43xx USB0 Host/Device/OTG controller
1
RST
Controller reset.
Software uses this bit to reset the controller. This bit is set to zero by
the host/device controller when the reset process is complete.
Software cannot terminate the reset process early by writing a zero to
this register.
R/W
0
0
This bit is set to zero by hardware when the reset process is
complete.
1
When software writes a one to this bit, the Host Controller resets its
internal pipelines, timers, counters, state machines etc. to their initial
value. Any transaction currently in progress on USB is immediately
terminated. A USB reset is not driven on downstream ports. Software
should not set this bit to a one when the HCHalted bit in the USBSTS
register is a zero. Attempting to reset an actively running host
controller will result in undefined behavior.
2
FS0
Bit 0 of the Frame List Size bits. See
This field specifies the size of the frame list that controls which bits in
the Frame Index Register should be used for the Frame List Current
index. Note that this field is made up from USBCMD bits 15, 3, and 2.
0
3
FS1
Bit 1 of the Frame List Size bits. See
0
4
PSE
This bit controls whether the host controller skips processing the
periodic schedule.
R/W
0
0
Do not process the periodic schedule.
1
Use the PERIODICLISTBASE register to access the periodic
schedule.
5
ASE
This bit controls whether the host controller skips processing the
asynchronous schedule.
R/W
0
0
Do not process the asynchronous schedule.
1
Use the ASYNCLISTADDR to access the asynchronous schedule.
6
IAA
This bit is used as a doorbell by software to tell the host controller to
issue an interrupt the next time it advances asynchronous schedule.
R/W
0
0
The host controller sets this bit to zero after it has set the Interrupt on
Sync Advance status bit in the USBSTS register to one.
1
Software must write a 1 to this bit to ring the doorbell.
When the host controller has evicted all appropriate cached schedule
states, it sets the Interrupt on Async Advance status bit in the
USBSTS register. If the Interrupt on Sync Advance Enable bit in the
USBINTR register is one, then the host controller will assert an
interrupt at the next interrupt threshold.
Software should not write a one to this bit when the asynchronous
schedule is inactive. Doing so will yield undefined results.
7
-
-
Reserved
0
9:8
ASP1_0
Asynchronous schedule park mode
Contains a count of the number of successive transactions the host
controller is allowed to execute from a high-speed queue head on the
Asynchronous schedule before continuing traversal of the
Asynchronous schedule. Valid values are 0x1 to 0x3.
Remark:
Software must not write 00 to this bit when Park Mode
Enable is one as this will result in undefined behavior.
R/W
11
Table 400. USB Command register in host mode (USBCMD_H - address 0x4000 6140) bit description - host mode
Bit
Symbol
Value
Description
Access Reset
value
